|
Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks
2 f' h4 Q' X9 z然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack
# ^/ s2 p0 n% g, M J$ T* X之後卻有如下之 Meaasge:
$ H8 }0 C) g1 Y; [9 W8 i# H9 Z: X2 Z4 [: ?3 a+ o- y
******** Pin Access Analysis ******* 6 y. P0 K) `8 }! S- H3 M7 p2 t
** # Cell Masters = 1000
3 E# T9 ]' Z0 J$ z" `' A8 p** # Ports (logical) = 2500# f; p# B" r- }' Z
** # Pins (physical) = 2500 ^1 S! C+ T8 s' Q
** # Pins with no good access point on Grid (V&H) = 5 ( 0%)' [- ^# o d! U
** # Pins with no good access point on Ver-Grid = 5 ( 0%)( b1 K7 h0 o$ m% K" n$ O
+ I& Y5 h) `( m" v$ w
請問下面這兩句是代表什麼意思呢?
6 U% g: W g' D& g! |; n" a** # Pins with no good access point on Grid (V&H) = 5 ( 0%)! z: P% N0 K# M% d7 t: A; d
** # Pins with no good access point on Ver-Grid = 5 ( 0%)( s! @9 N, f: k" ^; K+ M! K
" V2 j8 l" [ X, s$ y ]' n( O若是代表有錯誤的話是否要 Fix 呢? |
|