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AMD Geode LX 800@0.9W處理器
General Features
7 f$ \3 T( t% U( {1 |2 _■ Functional blocks include:3 U. V+ T0 F7 i5 ~- {
— CPU Core
( T3 u3 d% _; X& M— GeodeLink™ Control Processor
$ `# d+ }, n1 K% o4 [# l6 s0 Z3 l— GeodeLink Interface Units2 j6 b7 O0 N+ V# X( O5 G2 i
— GeodeLink Memory Controller
* w' a; N! l% }# P' Y— Graphics Processor; |) p+ u+ S( b. [1 ~8 x- ?
— Display Controller" j R; {* {8 X: r+ V$ P; B! u
— Video Processor* l7 [5 c/ r8 K" |
– TFT Controller/Video Output Port
- E6 C" A, [" e2 f, p# U* y [— Video Input Port
5 r Y8 u5 T* E3 l" b8 ?( _8 r— GeodeLink PCI Bridge
! y; J6 z) u! W+ d" J7 L— Security Block
# y+ g$ x( @; C8 L■ 0.13 micron process# ]% A% u2 R* H' x5 w/ i. [* e
■ Packaging:" x9 W+ Q: B, o4 Y7 s7 E, s+ C6 w+ ^
— 481-Terminal BGU (Ball Grid Array Cavity Up) with7 E! N5 g4 t- z/ c0 ]: i' e) H
internal heatspreader7 D- U& N* S1 `/ v: v
■ Single packaging option supports all features
* ?6 K' W) h' ]% \# K' FCPU Processor Features
; i, ]4 r# Y2 n Q& k/ G■ x86/x87-compatible CPU core
5 F3 i+ r( A$ Q■ Performance:/ x, G& r* z! |! }
— Processor frequency: up to 500 MHz8 w, n9 D- x6 t* \1 ?1 @; q- f. N
— Dhrystone 2.1 MIPs: 150 to 4507 M) a! [( u, ]* t; ~+ t8 S
— Fully pipelined FPU2 ]# w- B; d4 g$ c
■ Split I/D cache/TLB (Translation Look-aside Buffer):: I3 w+ C7 M+ S9 x8 M, P0 a
— 64 KB I-cache/64 KB D-cache
7 q4 H1 Y( T6 `! B% Y1 V8 q' G5 r— 128 KB L2 cache configurable as I-cache, D-cache,/ d, f! S* E8 n5 M/ J
or both& b0 l1 z* Y, k( M, g
■ Efficient prefetch and branch prediction) N+ ^+ a" d6 Q3 ~
■ Integrated FPU that supports the MMX® and
9 t4 o! O: O5 \- m# }) ~5 O/ I: m. V* [) JAMD 3DNow!™ instruction sets
$ ?. O- @0 f9 h: j* b■ Fully pipelined single precision FPU hardware with
1 S- G% y5 z9 Mmicrocode support for higher precisions& h3 l$ x. h" A$ A
GeodeLink™ Control Processor, `6 H& L9 F, r* w9 B8 I
■ JTAG interface:
2 O2 H% _! I- |' N C— ATPG, Full Scan, BIST on all arrays
( \9 g& {, Y9 C$ H# A— 1149.1 Boundary Scan compliant/ q: a- p4 j/ E- Z
■ ICE (in-circuit emulator) interface$ R' n1 {" g! h/ ?8 F. R; r
■ Reset and clock control) |' N) \1 {! l" }4 I1 \% ?( J
■ Designed for improved software debug methods and' _" F* _7 M4 j9 ?9 _
performance analysis8 u, S: W( V3 a; ?
■ Power Management: W6 {+ i, A8 c" n- j
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
& @2 C9 q$ [( B& f% m500 MHz max power$ G* q( i) B& k6 u8 o$ W# j
— GeodeLink active hardware power management
$ z! e4 ^6 y" o" S2 V) E& T& l— Hardware support for standard ACPI software power! }. G& e* ^, a8 L7 o. u& p% m
management2 F. k+ S- n. V- f7 d: O+ j
— I/O companion SUSP/SUSPA power controls
! @% ^ k Q$ P0 f— Lower power I/O
% [" ]- k/ j3 t$ J! \" L# m— Wakeup on SMI/INTR: |# b; a. M7 g. l% }
■ Designed to work in conjunction with the+ \! D6 V9 _% ` P9 {) H
AMD Geode™ CS5536 companion device6 @" G3 y C0 {. R9 i
GeodeLink™ Architecture& E8 I- W5 K/ i x: y; C
■ High bandwidth packetized uni-directional bus for
- s; F3 A! k* D4 \ j& ~/ }internal peripherals% c! R# \, [: Z3 S* i, t7 _- j
■ Standardized protocol to allow variants of products to be
& [. l- r* j7 n9 cdeveloped by adding or removing modules9 ?. d- l6 r3 h Q
■ GeodeLink Control Processor (GLCP) for diagnostics: ?* H$ t9 L8 j5 A0 d. ^9 _; J; [
and scan control
- `; G8 N; i* \1 [+ E■ Dual GeodeLink Interface Units (GLIUs) for device interconnect1 z0 d" N; v4 _0 | G% @. i. T- X
GeodeLink™ Memory Controller
4 ]8 {) A( L! x4 A' J& x■ Integrated memory controller for low latency to CPU and6 l# Q( o. ~6 i7 ^- l ^
on-chip peripherals
8 k3 L' f0 H. H( d% X9 w■ 64-bit wide DDR SDRAM bus operating frequency:' O. @5 x* B* I1 M9 f6 H3 ]
— 200 MHz, 400 MT/S' U) T+ |7 u' q! A
■ Supports unbuffered DDR DIMMS using up to 1 GB2 h7 n! f% _. M7 [
DRAM technology
; `; [$ F! c5 b2 s( H0 s8 Z■ Supports up to 2 DIMMS (16 devices max)5 M7 F9 @6 i3 ?9 }( k' L
2D Graphics Processor
# ]9 \1 e0 W& G( ]+ C■ High performance 2D graphics controller
8 }2 A' e4 a' H% `! _: L■ Alpha BLT* I2 ?4 t( U5 J
■ Microsoft® Windows® GDI GUI acceleration:
5 U" u5 L3 h6 a7 o" l6 b— Hardware support for all Microsoft RDP codes
& Q6 o; H6 }. f, T5 ]■ Command buffer interface for asynchronous BLTs
2 x3 J3 H6 U+ k; z" O■ Second pattern channel support
6 a" d/ t! q: G/ L" [3 q; q. H3 E* I■ Hardware screen rotation |
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