You must be sure that, ; w8 ~, c$ Z0 l, F9 N' S5 P" @1. your design output meets standard SVGA HSYNC/VYNC timing4 n& [( y: @. ]/ Y
2. You must also set constraint on the ISE project, and check the timing report after & ]) Z$ I3 S. e8 M/ }8 B the P&R is done. (also called STA timing report), k% u1 X; E' p& x: R: p, t
3. Sometimes, you must check the board, and I/O SSO issue(signal integrity....)