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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用2 H+ ~6 H9 ]8 N0 a+ H9 l! a1 M
Nwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.
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9 q( ]; u" [, d" ~, dDummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance
, R D# Z. y# `1 \1 F; S) fExtraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer
3 y6 s- m5 |0 b2 W# D; w% }dummy, 為的是在CMP process時,有較佳的均勻性:9 |, P4 V7 z" t9 D9 i% W; E- H
Dummy(or fill) metal is introduced in the interconnect process flow to enable uniform' _& z f) f, r* ]! l
thickness control in the CMP process. Dummy metal needs to be treated as floating metal 9 ?3 O: ~9 O2 V9 _+ D8 S
unless it is intentionally connected to a constant potential. Floating dummy metal ( I7 [' h; h: [: d
essentially acts as a capacitance divider.
: d+ G' R+ h% F0 D5 N另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆
7 [2 L% j( L3 ^! f! r$ Z$ _mos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保
" _" {: M/ l. c: o5 F5 P主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部
" T) H5 y; ` {* ~( l& c份).以上是我自己的想法,歡迎各位先進指教 |
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