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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用' q6 L q$ p0 }
Nwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.* N4 c- _, I- H! X
7 m9 N5 u4 g$ |Dummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance / [! B* ]) Y+ Z/ r0 E6 w
Extraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer
6 V: d: |6 \1 q7 |dummy, 為的是在CMP process時,有較佳的均勻性:& e2 B- C7 O5 R* g
Dummy(or fill) metal is introduced in the interconnect process flow to enable uniform1 p9 a2 h3 N; d5 I
thickness control in the CMP process. Dummy metal needs to be treated as floating metal
8 P+ C! S8 Q% n; E1 G/ G/ O9 V7 y& qunless it is intentionally connected to a constant potential. Floating dummy metal 3 Z2 j5 P: s9 `3 C, b2 h9 a
essentially acts as a capacitance divider.$ z: i- ?: t1 s ~
另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆
; {, i; j( n) B- O) ~; Z% Omos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保
! M! Y- b! D6 H9 P; V. |0 `. f主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部
/ c9 F% l Y; @份).以上是我自己的想法,歡迎各位先進指教 |
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