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8 Failure Modes, Reliability Issues, and Case Studies 228
0 Y1 e! r8 I) S2 }/ f8.1 Introduction 228
) x. F1 n' M9 c2 k$ o @5 A! t4 E8.2 Failure Mode Analysis 229
8 M+ o: w M3 e( {+ C! a: f8.3 Reliability and Performance Considerations 238/ z, @. T8 B" n0 J
8.4 Advanced CMOS Input Protection 239
: E; T' Y X% z5 M8.5 Optimizing the Input Protection Scheme 242' e ~* q! @+ h4 {8 ?7 c1 Z
8.6 Designs for Special Applications 249' g1 z1 u6 j/ n b) R0 W1 z# F
8.7 Process Effects on Input Protection Design 253
. Q& l, e4 d$ a8 g$ i6 E8.8 Total IC Chip Protection 255& E/ C* A T5 [9 R4 G! y6 F" l/ m
8.9 Power Bus Protection 256
7 x1 N: T. ~& {3 F S$ l8.10 Internal Chip ESD Damage 258
" F/ O, }0 E/ ]8.11 Stress Dependent ESD Behavior 263# `+ N4 ]$ S( n5 J" o0 U( T
8.12 Failure Mode Case Studies 267
. ^ Y' f, j$ _- u8.13 Summary 271
. l' k5 c5 y3 o4 b2 u1 ^: eBibliography 272! M8 e2 ~: C4 M# I. ^& _
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