Xilinx Virtex5 FPGA 結構與特性

小朱仔 · 發表於 2008-3-26 00:28:20

*Objectives
, }) E0 n) D+ R- v+ i( UAfter completing this course, the student will be able to:% w6 K( |. Y9 Y% w) m
Describe both the feature enhancements of the V5 over the V4,, g2 ^. }% U9 |9 K; _2 K
and
: y0 B% F, g3 FNew architectural features of the V5
  Y/ l3 @6 B0 p  |Have a fundamental understanding of how these features can be
  X0 ^  d& W1 S; j$ Oleveraged to bring about timing closure.: M, A' j# g+ t
*Agenda
8 E! C5 ~4 c( n2 j" XOverview (15 minutes)
/ d' Q9 e/ o/ Z6 h4 T# B6 T! VBrief Description of Differences between V4 and V5 (30 minutes
' Z, @8 a' ]- |7 Q& n$ MV5's new PLL and Use with DCMs (45 minutes)
' K; h0 [" X- T' {  G" U& HLab 1 – Introduction to the PLL/Architecture Wizard (30
' X. N6 Z7 b0 V. c4 xminutes)" x. P6 L" L! P! R' e0 K/ L  X
Improved Features in V5 (30 minutes)* }0 ^$ ^% B( {& d8 U
Lab 2 – Leveraging Improved Features (45 minutes)

hqioan · 發表於 2008-7-2 13:04:38

下載來看看...希望有幫助....最近在學

moneyhqq · 發表於 2009-1-4 19:31:14

hao hao hao hao hao hao hao hao

ch1122 · 發表於 2009-1-9 13:51:49

下載來看吧...多增加一點知識也是不錯...
感謝分享..希望以後有機會能用上

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Xilinx Virtex5 FPGA 結構與特性

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