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回復 4# 的帖子
1. Using technology file to create a library
: ^! {% p- A- P5 M2. Do stream in with cell type definition file. Specify some special layers' number. IE : Boundary Layer is 63.
b+ R: T) {& u- {6 w/ a* P3. Open new created library, and create some metal blockage if need.
. a. b; c: W2 d0 Q4. Do smash if need.
& \0 V* o$ o+ M# K6 y! T K5. remove some unnecessary extension txst. IE VDD ---> VDD& _5 n( U* L% E# _( z w: ?) M2 b
6. Define power,ground as well as in/out port
3 d2 j6 r# X8 k- x U% @+ J7.Extract Blockage,Pin and Via by using command auExtractBlockagePinVia.
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The processes listed above is my method to do data preparation. Maybe someone know other best way for this issue. Please share it with us.
1 R2 i9 a$ A _- f5 ^8 _( r5 x" I+ o-->我要怎麼做才可以把 ANALOG中 重複性較高的部份交給 APR去做?$ J# K* j' E: K, T0 y8 X) h6 f
I don't understand your question. Do you want APR toll to place and route your analog block? It is a bad idea if your answer is yes. |
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