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回復 4# 的帖子
1. Using technology file to create a library! D' P% Y/ V: V5 U `5 v3 K) F: K" w
2. Do stream in with cell type definition file. Specify some special layers' number. IE : Boundary Layer is 63.
9 z1 ]; [9 n! l3. Open new created library, and create some metal blockage if need.
- s+ @2 B- ~+ }1 j" w0 F8 U4. Do smash if need.7 Y3 B2 ]. I2 F( s
5. remove some unnecessary extension txst. IE VDD ---> VDD# l3 K7 J4 Q3 n( Q1 C% |
6. Define power,ground as well as in/out port
, H% @' o# z+ j- i9 u/ {7.Extract Blockage,Pin and Via by using command auExtractBlockagePinVia.8 J! e8 b E, V# Z# f
8 g1 ~/ N. Y. I# Z0 j& x$ F4 ?The processes listed above is my method to do data preparation. Maybe someone know other best way for this issue. Please share it with us.
! v7 x8 a' A2 Z-->我要怎麼做才可以把 ANALOG中 重複性較高的部份交給 APR去做?# v; V) G- E' p/ u: Z
I don't understand your question. Do you want APR toll to place and route your analog block? It is a bad idea if your answer is yes. |
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