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發表於 2013-12-12 09:14:21
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Senior Physical Design Engineer% m. w3 q& x7 N/ J: }9 W0 R
公 司:A famous IC company l% j) A6 I0 `) G. s
工作地点:南京
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! X4 v$ G; @8 J; lKey Responsibilities
" {2 j( Y& a, l) w. n8 G- o2 U- qDepending on experience, key responsibilities will involve some of the following: + ?8 N# L/ q5 k3 f, Z
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. 3 C. |# K6 M# I7 M, e+ V7 h
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
, [9 D+ ]+ j; ^Leading a team of physical design engineers and resolving the technical related issues. : D, K a# a) a7 l2 [ d
Crosstalk analysis, power analysis, and static timing analysis. " n7 n' G u5 ^4 p$ J. [$ T
Write scripts in Tcl to improve productivity.
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职位要求+ L0 G$ ~# F( Z; u \" H& N
Experience: 5+ years in physical implementation engineering 4 A- @, u0 {: ?
Essential skills
: t/ a t. G. {) Q T6 L2 v4 MMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
+ _' x5 L( E( Q N5 V: r* TExperience with Magma or Synopsys place-and-route tool set and physical design project implementation.
4 F8 s( P# H: F0 |* n; JGood programming skill. Capable of writing Tcl or Perl.
& n6 L7 d2 h! vFamiliar with synthesis, static timing analysis.
8 K% S# \" w4 l* @Self-motivated team worker, good verbal and written communication skills in English.
3 m3 O2 ^. I) X @" @* S5 F# hTechnical and team leadership proffered. Previous management experience highly desired. ( t1 u9 E& w( E7 [$ M
Experience with synthesis, DFT, and verification is preferred. |
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