11/19-20 Semiconductor Manufacturing Forum 2009

chip123 · 發表於 2009-10-21 17:58:10

由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。

2009/11/19-20 National Chiao Tung University Library International Conference Hall
交通大學浩然國際會議廳

Agenda 議程
Session 1: Thin Film (11/19 13:20-16:20)

; I0 [7 s# X! K1 G9 d6 V* C# U	Topic	Speaker
13:20-14:00! Y3 `5 ]9 M! c: [6 ?	Engineering Slurry for Copper Chemical Mechanical Polishing ; b) B1 f6 J8 ]* @	Dr. Song-Yuan Chang / # S8 w: F+ q. G2 f CTO& senior VP, UWiZ& t# s# Q4 Z5 a Technology
14:00-14:40 ( t! \|) S- J9 I7 w4 N	Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced Nodes	Dr. Fred Sun / Cabot$ B/ ]2 R# W9 B* s% j8 n2 \( H. Y
14:40-15:00# q' q7 m3 t. I- N	Break+ G* M, X; ?" C. i, r' D	0 m0 z) f9 H. c; [( d i6 b
15:00-15:40 . B- Z" p r D2 @' @	? 9 G" ^/ s/ L2 j$ n" N( j6 g1 w8 e	Apllied Materials }1 E/ J1 W5 ]1 s
15:40-16:20 $ u9 F5 z9 k. }& z% u	CMP Fundamentals and Implications for Consumables Design S. ^; V$ V) a. v	Ms. Kate Kao/ Marketing Manager Dow chemical 9 A# x/ t7 E" x& M: t

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chip123 · 發表於 2009-10-21 17:59:25

Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)

. E2 h6 O% `! V	Topic * t( ?1 `9 s* J5 \& n# }* B" u# U	Speaker9 U7 D; R* D2 b8 a" R& f* E1 j
13:20-14:00# c3 V3 I" C8 u4 D5 P: F	Sip Assembly technology? 1 F( g# L O* D	Dr. KC Yee/ VP, ASE * j+ a6 H: h; x" d- g* [
14:00-14:406 w5 w7 K" z% t* h	Assembly trend from perspective . L" s8 G& a: I/ @5 G ~- k	邱世冠資深經理/矽品 9 V* d! t- c: ^1 P- A前瞻科技中心 7 d: ^ i3 S0 `* Z1 W( s, E
14:40-15:00 9 s; \; {& e! a1 A+ K	Break( ]( {9 G5 I- U+ F: c. ~	* u1 ~ [9 m$ d
15:00-15:40( X+ k y1 G: u1 Y- F7 O	The Paradise of Cost-Effective Wafer Probing Technology5 \|; v7 }0 d0 g' v$ B( E0 n$ Y L	Dr. CCNi / Associate Director , KYEC+ Y3 q3 x' G; I. f* H9 \|. {: r2 v
15:40-16:20 1 t5 c6 w; l9 D3 ~% l	RF SOC /Sip?% R6 d4 w9 t1 X, ]	Verigy6 t2 }$ y4 G+ d& v

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chip123 · 發表於 2009-10-21 17:59:56

Session 3: Design, Reliability & Testing

* G! ^6 T/ }* X( a	Topic 8 ~3 B/ f) A- v$ _" P	Speaker # z, R9 H! D; i
9:00-9:402 v( J# g) X) u: S5 \	Design Trend?. z8 i! x9 T4 Y/ H	Marketing VP, Dr. Chiang Alchip 7 t+ B) ]5 q& m9 \|. H
9:40-10:20 % ~: m" h( l0 F	Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits 2 n% d$ s/ w" h	Prof. Ming-Dou Ker / I-Shou Universit ! \) X$ }- P$ _# G! W/ \
10:20-10:40 / V$ g% `0 E4 A	Break: Q2 @4 K5 K8 K	) \|5 ^0 c# d: c' T' l7 {
10:40-11:20 ! K' K9 j* _) [8 s	Parametric Test Challenges of the Next Process Frontier 4 x4 n/ ~' q$ C0 c% P/ _	Ms. Flory Tsai / agilent 9 l m( d2 e! l% @/ i N3 g
11:20-12:00* z0 R* E. ]! M6 t. x	Recent Development Work and Trend for Semiconductor Device Characterization 9 ^( \8 x9 R1 M* P	AL Feng / 專案經理 / Keithley Taiwan : I) e! y: J( t

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chip123 · 發表於 2009-10-21 18:01:32

Session 4: Diffusion

' R) d; X: I% x( Z! d	Topic 5 v# m# f4 o. R8 J# c3 ?	Speaker' k$ s* p5 S, R5 l; F
9:00-9:406 G& G! b5 o% \# \|8 T4 y0 R	Surface Preparation process control requirement to support CMOS scaling into 22nm P- v2 G! V. k& o/ a	Dr. Scott Becker/ Vice President, FSI 7 K6 X" l3 ~, S
9:40-10:20* G! i' z, ~; d( M' X	Wafer techincal roadmap and application for advanced or special proces ! x( Q! E1 \& I	MEMC . b( a: ]; h1 h1 I& R
10:20-10:406 ]$ r5 q8 L2 a; p7 j; a	Break # @1 t+ G: S, O5 @4 }0 n- h Y	7 W/ v. p) w9 G+ }2 A
10:40-11:20 * \6 F6 i" N& W7 U	5 U7 v% J+ R# j	3 w- Z! i% S# r! d; W

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chip123 · 發表於 2009-10-21 18:02:03

Session 5: Litho

5 d) h6 v, W, a! y0 _	Topic 1 }# l8 c9 \|: ?	Speaker & l" s' W' Y& O) O. E# D
13:20-14:00 " e0 Z; ?* f* \|' ]9 `% ~8 B3 f	Photomask technology for 32/22nm and beyond% j* H e6 }. e( b9 \|	Dr. Hiroaki Morimoto/Senior General Manager,; s9 V* C) G& j9 y Toppan Printing) L) {. u+ f7 E+ E- `7 y s, f
14:00-14:406 a$ P7 n* \# r* t: I$ K	' _4 B& a8 c' t0 Z% a) r% [/ DImplant Resists for Advanced Node Applications r9 u% h' n; w- ]) X	Mr. Yoshiro Yamamoto/ / h8 u" T+ U. PDUV RD mamager, DOW % {! l/ s9 H" ? @, r9 A7 k) q- F$ x/ y Semiconductor Technology + q5 _( C" l, o! }
14:40-15:00 ; f2 b, i+ T0 y4 y	Break & ~: B! Z, D3 x! \8 w	8 E9 r8 I: k: m6 D# e
15:00-15:406 m7 }' g* H* K4 n+ f	State-Of-The-Art Development of BARC Material 5 D3 W! s! W' F$ r3 w	Brewer Science 9 T- r p% Y8 C; \|' v% b7 I( Z
15:40-16:20 ! }& M0 o% l- Z6 p$ v	The Future Trend for Next Generation Lithography 2 \|$ L7 R) K. d3 \|5 p U	ASML; a; T2 R( O6 G9 \# n/ u" X8 v# T% v
16:20-17:00! z7 J7 G5 z0 j3 f8 T" v5 c	Future Trend of Track Technology $ a! ~8 V+ n! y1 y	TEL 6 Y+ \/ ~! B. _0 l2 A0 k

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chip123 · 發表於 2009-10-21 18:02:34

Session 6: Etching

' ^1 ^: H/ S" j	Topic, \, _9 R) I5 \4 U0 Z	Speaker s/ K8 u% g! \% g4 A6 w) B
13:20-14:00 6 U$ s: E: D. q0 D	The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer ' K0 F( \( l0 Z- o9 N	Mr. Shay Tina / CI Semi , Director of Sales * x0 ^7 Y. R& s1 l
14:00-14:40 5 p1 `9 K2 @# H& s b6 y	Green Chemistry for current technology and beyond $ Z/ v4 h9 o+ w/ b# o7 }	Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager& z3 e% S4 J: P3 j& g! z' Y2 G
14:40-15:00, L3 r$ ?* _" `4 l j	Break& `" {1 a8 }( K	7 q, `4 Z2 R! X2 @, M9 W
15:00-15:40 0 R* g: v& j/ J8 d1 ^- \' u+ Q3 `	Post-etch residue removal for advanced copper low-k device , T* t O; }0 y" V7 A	Dr. Hisashi Takeda / EKC Technology, DuPont # N% t# K% F0 @% j2 W
15:40-16:20* P8 g5 K9 J" u: M	Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean 9 F/ {2 l) [/ W: U+ C1 `, e	Lam Research5 U1 c, r4 F4 e% \|6 c" l y' ~+ b
16:20-17:002 X' [& e9 `: G	Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications / r Y% I9 E _	Surface Technology Systems 7 a. H4 W( u1 ~9 \|: b! t

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