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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題) u; I% K( d: B9 M8 \$ i
1 r- \; N* d- t1 O/ ^4 b/ R8 o
請教業界各位先進. a- b: S, E5 r: Q% `1 V
目前的chip開發,需要多少投資?1 G! Q6 g' F6 w1 s8 ]
首先是假設 Febless design house.# O* s+ r% {# v7 W1 I; B  \
自家由algorithm 到 RTL simulation 完成
9 A( a+ x9 b* S  L( V後端包給 backend service 公司 (layout, mask, Fab, assembly..)1 J+ c2 x3 c7 u- M
以 ARM9 or ARM11, AMBA2.0 為platform
# o9 f% b7 v# \' B6 d. n; l$ e那麼7 i0 A9 q- q- t  n: w
  (1)90奈米, NRE大概多少?
9 n/ M6 |$ S- P/ N' }4 U  (2)65奈米, NRE大概多少?
- e  b. U  x/ D  }  (3)或是您知道其他製程, NRE大約多少...
9 i$ \! n) B8 b/ b$ ~, X
: L7 Z1 _5 O8 v. t/ ]$ i謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?! X( o5 n4 q9 K7 t/ E; |
How many mask layers it will be?
# K+ Z' ^& q, O8 h4 R$ iBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
6 L! U% ~* H# W+ h  HHow many chips you need? A full set mask or MPW?
8 _+ {* Z% c, @' M  w5 {7 |9 tWhat package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,) |) i3 R6 {* }
2 G$ f+ P% I; i! P
I just estimate the investiment of a ASIC team.; k$ f9 q! X* w3 J' A
not servey for a project.
1 _9 p6 }- L, n% d6 A/ u8 zSo, I just want to know the range of NRE.
( X1 G/ h- e: E: g9 i6 l
" d" F+ O1 P) u) G+ B( f2 t5 KFor example, It will be
; R% M4 @* D4 _+ H# C(1) 5,000,000 NT$ ?
- B, l" @+ d! G, m* R; X( w(2) 8,000,000 NT$ ?
9 i6 b' [5 V6 A+ B: W(3)10,000,000 NT$ ?; d1 Q3 h( |( @
(4)12,000,000 NT$ ?
5 d! J, f$ n# c/ |+ }(5)15,000,000 NT$ ?
! i: G1 }5 G1 b1 b3 g: B2 a6 z5 s% K! q  a
Sure, I understand following things:; E% p6 v+ q# r5 W1 \
- full set mask cost more. s& ~7 I8 [4 P, P* W8 n4 t" q5 U
- PLL/LVDS... analog IP are extra cost
# f2 F$ i0 E# D: a9 e, b+ e - pin-count and area also influence cost
$ h: e- Z" P8 v/ W - different package also cost different- L5 f- {+ M. ?8 c1 j4 Q
* ]$ g- z0 o) o
Therefore, if really need information for estimate,
7 R, U0 I* F% X1 V* Z( z7 N# Djust for example./ U& p) }; x: \+ z" r' t
Let's assume a SoC for FullHD TV application
8 b, _0 V" k7 x2 Sit will include3 s! {* A9 _" [; p  M1 ?
  - ARM AMBA
3 X; i  }$ f+ k  - DDR2 I/F
' p) J% o4 _; E  - GPIO, IIC,...  H9 U; R9 m) {5 g
  - LVDS out (dual link)
1 E5 R) h. N! W+ R2 z8 }& i( Y! D  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
. E8 G6 a3 i0 G4 w& r; h  - 12bit ADC, 10bot ADC x2; v4 O$ C! e4 P
  - PLL/DLL
% G1 K* W/ H6 F$ P/ a  - 256 pins 以上
* d4 S; s* Z7 D; q! G& X4 m7 f% D) S) u% @- I& u8 p
Than,... any idea about NRE fee?: U' u" d5 O, V: d3 P# |! U
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,& O; a9 u- ]3 d) U7 d6 d7 V
basically 65nm-->USD$1M above and 90nm-->700K above
4 Y+ I& w6 ?5 L4 q: M2 ?and base on different foundry has difference price!
0 [7 n; I: X( l  o1 b2 c6 lthis price did not include any specific IP like TV encoder, decoder, vedio codec....
, E2 K) t* j& rand did not include the ARM licensee...: v. c/ s+ U- k- t' o" A. V
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
5 E/ }/ c& b! E3 L; B: Fand package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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