Bit rate and protocol independent clock and data recovery $ e5 J: y" P9 [ J/ T ) u, u% t5 N8 }' C$ J: S8 b* L! J0 c" o0 p7 v$ _
Abstract 0 j# W9 E$ B8 z7 o% T: V* e( S2 R$ |4 V+ F
A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use ) i1 v1 g& x' X9 v
2 [& o) h' W: m% Xin optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been , `1 f e: x# N1 U! Y' Z0 S' P2 ^# P& Q; K
extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). 9 m4 }% f% e8 [% v
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This architecture guarantees reliable clock synchronisation of the input data with different line + `$ A7 z+ ^9 r9 Y ^5 M " c6 w. [0 |0 q7 o3 G* icodes over a frequency range spanning multiple octaves+ g. F8 u5 d2 [& o* n
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建議shangyi分享IEEE下載的論文 8 g. `- s! R& b. ~7 k9 d ^最好想辦法把每頁最下方的東西弄掉8 x2 Y/ d- j6 m1 d/ y1 P( Y2 d
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這樣IEEE就知道這篇pdf檔案從中原大學流出的