LVS問題 望大大指點

xjyy

使用LEdit90的LVS時，顯示This file is Binary.LVS can not perform iteration.無法進行對比，這是怎麼回事呀

m851055

是比對檔案中路徑的問題，若有需要詳細說明把netlist PO上來................

xjyy

原理圖
* SPICE netlist written by S-Edit Win32 7.03
* Written on May 27, 2009 at 16:57:24
. W$ u$ y3 [2 a* Waveform probing commands
.probe
% p( H1 ?7 A. q.options probefilename="G:\tanner\Nand2_1.dat"
. {3 Y& Z, a4 W- _. M+ probesdbfile="G:\與非門2.sdb"
+ probetopmodule="Nand2"
/ e" h- f" G( W! f4 G7 G# X% C$ S& A* Main circuit: Nand2
M1 OUT A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Gnd B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
% p  H, C" h* r" F8 k2 l. LM3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
7 t% ]0 ~, Y) x( |  X& C6 a) K+ OM4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
/ U8 P3 y  @5 D3 U7 b3 e$ p* End of main circuit: Nand2

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版圖
* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;
* TDB File:  G:\tanner\Nand2.tdb
" `3 a3 z5 H2 a! k0 t* F% t* Cell:  Nand2        Version 1.07
* Extract Definition File:  G:\lights.ext
* Extract Date and Time:  05/25/2009 - 15:05
( Q$ d1 u% S. d, k+ _7 r* Warning:  Layers with Unassigned AREA Capacitance.
*   <N Well Resistor ID>
1 L/ R+ ]0 c0 A/ j/ F*   <Poly Resistor ID>
*   <Poly2 Resistor ID>
$ J% ~& p1 i# z' p) B+ K3 e6 \*   <N Diff Resistor ID>
9 K- p1 Z. x! o" P+ B*   <P Diff Resistor ID>
9 W$ p0 [5 i8 i$ m5 W+ P*   <P Base Resistor ID>
* Warning:  Layers with Unassigned FRINGE Capacitance.
*   <N Well Resistor ID>
*   <Poly Resistor ID>
" J8 Z3 I8 I# c4 Q. S* |1 U*   <Poly2 Resistor ID>
4 m1 X$ }, Q1 D/ I+ V+ ~*   <N Diff Resistor ID>
6 S. v, f, p7 }& A3 ?*   <P Diff Resistor ID>
*   <P Base Resistor ID>
*   <Pad Comment>
5 j, L$ B# ?* R  d* A9 b*   <Poly1-Poly2 Capacitor ID>
* Warning:  Layers with Zero Resistance.
*   <NMOS Capacitor ID>
7 V  n# H2 h: r) ^; L/ Y3 m*   <PMOS Capacitor ID>
' Y$ Z" L8 l! T6 H  |*   <Pad Comment>
*   <Poly1-Poly2 Capacitor ID>

* NODE NAME ALIASES
*       1 = B (12,-14)
*       2 = A (-16,-18)
*       3 = OUT (-2,-21)
4 T1 b6 D1 a4 f( r; f; l*       4 = GND (-30,-35)
% T! q5 h& @  ]7 t& I, o*       5 = Vdd (-32,14)
M1 Vdd B OUT Vdd PMOS L=2u W=6u
* M1 DRAIN GATE SOURCE BULK (3 -3 5 3)
  E! V8 U7 a( V2 t' uM2 OUT A Vdd Vdd PMOS L=2u W=6u
/ ^; m/ e( V/ g6 L! e2 J; D* M2 DRAIN GATE SOURCE BULK (-5 -3 -3 3)
$ y" @0 x/ L- IM3 OUT B 6 GND NMOS L=2u W=6u
* M3 DRAIN GATE SOURCE BULK (3 -31 5 -25)
M4 6 A GND GND NMOS L=2u W=6u
* M4 DRAIN GATE SOURCE BULK (-5 -31 -3 -25)
* Total Nodes: 6
* Total Elements: 4
* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
. x9 `: s6 Q/ n( z% {5 n  C3 u. v.END

m851055

與非門2 files name改為英文名稱.......................

xjyy

我宅了一周 沒想到栽在路徑上  萬分感謝 ！！！！！！！！！！