Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes
: U) g5 P# ^& S$ {
Karan Bhatia and Elyse Rosenbaum
& k' m. W8 [* s2 o( b# q5 QDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
. A  V6 [- R6 ?$ [. {9 o1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu

( w/ s# \- j  l; |4 t6 Y3 z! VAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
. D9 F5 \9 s, n, {" R* b2 O2 ncapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
  i, M& _  [; E) s5 |3 o/ [) operformance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
I/Os [1]. Layout-optimized ESD diodes provide a
high protection level per unit capacitance (C),
minimizing the performance degradation they induce
on high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼

- r0 \8 ~& I3 o讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
# f" ?8 X! C; [" J" \* v/ k真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
( N3 m+ E3 @# J- t; }: q7 }# I  T小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
% y# S- d1 z4 j, U' h; I現在急需esd的防護方式