在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

賴永諭

書上都有講哩...加油看看先....
& B; h) }  g# H6 E" T2 \, S8 F. t應該不難找到哩...

jasonxilion

gain margin is not considered in pll design？
i don't think so.
isn't it dealt with the stability?

kmchen3089

回復 #1 option318 的帖子
% {: y+ m9 b; K# Y(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
pll ,且亦有unstability issue
(see Charge-pump phase lock loops paper by Gardner
# A. _: g3 @  y. B" N6 B& nIEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
2 [$ V! O7 t$ J7 [5 D. J( M(2) loop BW is related to jitter (or phase noise) ,and locking time
* N2 Z( \- B# k2 Yso you have to consider loop BW  from jitter & locking time  spec
' o! E9 r! D( {7 n3 |' u(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
$ r; a1 C0 O5 m! w3 }* P- F(4) In my opinion ,gain margin is not considered in pll design