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Software Support
7 P q1 m$ Z4 l! O( V! [/ J; L- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
l$ n7 ]- ~& I2 S0 R( D/ s
( O3 S3 \. `/ R q7 Q: ~Platform Support 2 l0 Q' W; l. J4 K
- Microsoft Windows XP (32 bit)
& J/ |6 c# W9 m6 _$ J8 }% K% J8 \4 K+ T; {4 R. o. h4 i) h
Device Support . x. U1 i+ t3 J6 o
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. 9 Q& n: \0 a# \8 W2 i. M
0 v6 Y% W+ g/ | b% W- t* x/ zNew Features . W3 k8 d* N: Z+ z2 w% p7 k
General New Features and Changes 4 I; p6 `/ \5 [* G/ \! g+ B( n
- Supports "Create New Memory Part" for all the designs. 5 s& v+ r9 V3 Q% D
- DDR and DDR2 SDRAM designs for Spartan-3A.
6 q/ ?6 G" x* a+ ?5 P- DDR SDRAM is supported for Virtex-5.
' [, S3 \( C4 V* u7 h3 w- f- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM.
9 H( Z( |7 a7 d1 Z- MIG now pops up the design notes specific to the generated design.
4 z0 {' v" b) a8 i2 w/ {' g) P- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.
. u7 c5 g6 J# G- L% N' t6 o4 w- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. : o- g: h7 _( \7 T
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
! I. d* X# F9 X# W( z' O- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.
. Q y# B- V' g7 V* l, @- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". 7 p" p5 c7 ]7 Q' a% t
- Default setting "DCI for Address and Control " is changed to "unChecked".
: }0 D b8 p. s+ Z `: y, V- Frequency slider is changed to editable box in the GUI.
* \* [5 G; d) c0 u- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names. ; @ K8 V& s0 Z
- Removed console window when running MIG through CORE Generator.
* I$ b1 V7 O$ u: X. F; i- WASSO table (Set Advanced Options) accepts only numeric characters.
: |' V0 n g z1 O+ E- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. ' m8 a) N) m6 H8 t! e$ R4 m
- Provided web links for all XAPPs in the docs folder of the designs. + f! W: c! Y( z* E
- Provided link to Data Sheet instead of Log Sheet in the output window.
' ]4 j- |3 K5 d7 P9 I# f- M" F! Y- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window.
5 Q) l2 A* p! g- R/ G# D* C2 C- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank.
7 f% A5 ?/ t8 K# f- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition. ; e. V/ H/ D" G5 `' x
( K9 J& S/ @/ E$ l) \ ?Virtex-5 New Features and Changes ! m. r$ h' o# T J/ T7 U( i r+ x
DDR2 SDRAM
. ?/ H+ n1 P/ `! o9 B- New controller with several high-performance features. All the features are described in detail in the Application Notes.
+ Z$ g2 Y6 W% x! a9 |0 k1 x- Enhanced data calibration algorithms for higher reliability.
% D% q @0 A+ r- Bank Management feature is supported.
# A7 Y2 @0 x2 @0 ?- Supports VHDL. # q! ]2 R' K7 M5 h* i O" X; A
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
& c- E! I( |, O! F* L- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
' J! m8 Y* F" f% n9 g- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions.
* N) w. Y }: { T. j/ j" ma. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
1 Y& Z/ m. i5 K2 }. E( j a( Gb. WASSO is applied to all the memory interface signals. 8 O9 Y+ N0 G" m8 Z b( Z
c. Signals such as "Error" outputs are not part of the WASSO count. # Q6 g+ M1 h9 b/ Z5 M, W7 Y+ B8 n
3 T& [ Q& s5 P- B
DDR SDRAM
' ?6 d4 G- Z* B- This is a new design for MIG. Supports Verilog and VHDL.
- `+ A8 D& v( w7 e% ^- Bank Management feature is supported. * D' a3 Y6 Q5 h0 i
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. ; q% ^; Y4 M! C( U9 |/ j! ~% A' S
( D. D- W- o* ]2 B$ [, F
QDRII SRAM 4 Z$ @* V0 U+ O3 }3 U( {
- Added support for VHDL.
" x5 s- ]' V6 Q* S2 I& S+ G' s- Added support for 72-bit designs.
# Y5 S4 Q8 t2 R- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
+ B5 C Q" t+ ?7 o- i- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6
. f* c2 {- z5 T+ e- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. ' Y7 ?' ~ N) |9 R! h! A
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. - B+ U0 \& O: R- a0 r+ \/ O/ g
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 0 O K" D1 z$ B" f6 |( g
b. WASSO is applied to the output signals only.
! i# p* @8 z% T
& X' f; ^# {; |. a8 k+ }Virtex-4 New Features and Changes & b* s8 L+ ~( m. T% h
DDR2 SDRAM Direct Clocking
2 L9 U& s4 x: W! k" W- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
) I4 L8 G6 ?( a g- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. ( G( K- U2 `. r7 H7 R& L
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. * l5 I/ G% h: E
- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. 1 {0 z+ @4 Q: Q
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
4 J. A; K; g0 J8 h% u- Removed all TIGs in UCF. The reset signal is now registered in every module. + q+ c5 C' Y: [% p, H# G
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
3 l: D8 ~; I: {8 K- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 9 n, |$ _8 v' H6 T$ ^3 S9 X2 {3 `/ h
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. $ Y& ~6 Y* h. H0 ^
- Replaced `defines with localparams for Verilog. 4 B8 g, j& v2 o1 U& D! ?
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 6 o/ G U& E" g
- Several state machines now use "One-Hot Encoding". 9 z) P5 |- E4 S9 ~7 }% w* i
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. w5 @4 ]# A+ Q# n; I7 l
- Signal INIT_DONE is brought to top module. ; a( P1 @2 ]% x4 W: y$ e
- Removed the UniSim primitive components declaration from VHDL modules.
' t( ]/ M6 M; k, [- We now support all multiples of 8-bit data widths even for x16 memory devices.
) Q: t' S6 d( E& O- We support memory devices of speed grades -3 and -667. 8 t e! f, }; T! Y$ a2 c
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
+ n3 n- k: ]4 a% l. g |& \a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
% v: y* ~6 V( J7 n8 l& r9 `1 c6 N9 Jb. WASSO is applied to all the memory interface signals. 8 G9 j: o* X1 q6 N* g: O' B6 ]5 s
c. Signals such as "Error" outputs are not part of the WASSO count.
5 i; O3 k8 l' J+ h# a9 d1 m- H a2 v& e- w. N* s% i# ~5 j
DDR2 SDRAM SERDES Clocking
9 A0 ?; M5 l9 C& A8 x$ L z( b- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
4 s& w7 ?: t0 [& }0 X6 q+ f8 v5 r6 z- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
9 {8 B" i' p' o% [3 r- Support for ODT. 5 }- K/ D* Z7 [7 A+ d K
- DQS# Enable is selectable from GUI through Mode registers. 4 |# X# C1 w+ d
- Removed all TIGs in UCF. The reset signal is now registered in every module.
" Q: i* e3 g8 z) N ?" K- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
+ L7 M* i# X) \" @. n- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 7 ]9 t( ]: M+ i3 t9 F% Z& h
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
9 Q; N7 M2 q1 O9 \3 @) }- Replaced `defines with localparams for Verilog. 4 q3 N [2 Y/ h
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 1 ]3 }4 {. f" V1 [% H8 x
- Removed the UniSim primitive components declaration from VHDL modules.
! f. t2 x. H" M; l1 ~ U e- We now support all multiples of 8-bit data widths even for x16 memory devices.
7 p. ^9 r; ^* p e- Signal INIT_COMPLETE is brought to top module. 0 d2 r, R) `1 T& O, C$ t. `. C
- Memory devices of speed grades -5E and -40E are now supported. & S$ t+ @) K6 x2 k" C( P
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
) C7 l9 X, h* F* w7 _* p2 Y; `a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
0 |0 }. C& L( T ]b. WASSO is applied to all the memory interface signals. 8 i7 N; Q% g- n/ ^# G- Z$ w
c. Signals such as "Error" outputs are not part of the WASSO count. # N. t% B) n- J7 g
8 z5 `/ I: _, L, Q6 e/ w
DDR SDRAM
7 @; Z) ^* F9 E! K- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 4 X8 f; h0 ]( J. R0 g
- Removed all TIGs in UCF. The reset signal is now registered in every module.
3 F, M* V& a0 y" H& O8 @- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. & V: v r' L6 |
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 6 O, l) C" P7 m f) J, n3 C
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 1 o: m$ r6 ?; l" {( \
- Replaced `defines with localparams for Verilog. " r5 R) ?+ G7 S9 Y3 w
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. [6 t: j! w7 a; h
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
5 ^4 y( }) `( @7 L6 Q v3 P: w: J% T- Removed the UniSim primitive components declaration from VHDL modules. * u7 z* v7 w# o$ n# T
- We now support all multiples of 8-bit data widths even for x16 memory devices.
- k9 K9 T' Y) F0 v) y- The signal "init_done" is now a port in the top module. # _1 y/ C5 w! j, G. Y+ D! D- I+ i' h
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
! U& D* O9 Y2 N5 x9 x1 Sa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 0 u# l# I1 e: N6 b9 s' ?
b. WASSO is applied to all the memory interface signals. ! c3 f7 M4 [& {. Q
c. Signals such as "Error" outputs are not part of the WASSO count. 2 H( r$ P9 \- l; y- ^
" o& B( |7 A. N. H' u0 L# D; \5 I. ^
RLDRAM II - _4 @3 S9 s+ L8 X8 @2 N6 R6 {5 G. G
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. / a o# I' ? i w; W7 @
- Removed all TIGs in UCF. The reset signal is now registered in every module.
! t! [6 Q7 i. a; H- The design now uses CLK0, instead of CLK50 and div16clk.
' Y0 a; \( K. k! p1 x; e) @' H- CLK200 is changed to differential clocks in mem_interface_top module (Design top). * y7 f* z4 P. C* W
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. 3 p+ K4 b/ d7 s" c( t7 h/ C5 K
- Removed unused parameters from the parameter file.
6 }( P6 R$ Y6 r u/ T+ C f5 w9 o- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. : @- Y3 m/ s/ Y- \
- Replaced `defines with localparams for Verilog. # w C$ m0 d7 Q$ C" |
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
/ _, g* M- G! u+ d- Removed the UniSim primitive components declaration from VHDL modules. * m3 q. l9 X& {: v6 G
- The signal "INIT_DONE" is now a port in the top module. ( h# o: ~. l) e5 C3 w9 ]
- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. * \+ H. ~ _& ?
- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.
- S) R$ K3 X+ A, W" ^- G. O2 D- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file. 0 B( O- T- N5 b. X7 ^$ A/ ?& v1 Y
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
- X+ C; ?" Z$ b9 }$ d, K% S, u8 ma. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. $ x$ f5 R) `2 V: d5 H. K
b. WASSO count is applied on output signals only for SIO memory types.
/ a: R$ T" N c* E0 ~c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.
d4 `, C) _) w: T% E1 w9 A: l
: t# Y& A6 w1 R# {% QQDRII SRAM
# o q2 L- ]" z) h0 ]- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. " V& m6 J/ ]3 r* w1 `
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic.
: l9 R/ c- Q4 Z# ?; B- Supports generation of designs with out DCM.
, C, r% ~+ i: W! P- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. 5 w: g5 V7 b( b& a; }- N& ^
- Removed all TIGs in UCF. The reset signal is now registered in every module.
* B) e M) f- x3 t& {2 d* a ~" R- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
# u8 a$ i' u" s8 f+ Y( I- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
/ h3 M% x5 U! _2 d- Replaced `defines with localparams for Verilog. ; D9 T' N7 m# p Y: h3 {3 Y& Q+ u
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. , X; C9 a1 [/ ?0 X7 e, A
- Removed the UniSim primitive components declaration from VHDL modules. + J' L4 v% I9 J6 X& q
- The signal "DLY_CAL_DONE" is now a port in the top module.
5 v* S& j, l, g6 \# T) g) R* U- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. + A5 }! [6 H1 f
- Added support for DDR Byte writes.
4 C) v5 J' L8 |/ `5 j M- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
' ?. @# K5 i+ I& S4 C: w" p' p" ]9 Ba. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
4 v* Z0 K- v# X; E7 [1 xb. WASSO is applied to the output signals only.
0 Q/ x- I1 l; |% }+ W2 c" ], x9 oc. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. 3 v7 P9 t( q- y
2 R% `/ L# h7 [
DDRII SRAM ) B& U" U4 J6 J% F' _5 I4 \
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. : s0 E6 {, ^2 ~# V. Y4 m$ X) a
- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic.
' r4 ]) W8 l# }3 b- Supports generation of designs with out DCM.
/ y7 g2 H& f0 Y6 v* t- Part CY7C1526V18-250BZC has been removed from Memory Parts list.
; c# j) U5 ~0 r# Q/ H5 {& J7 H- Removed all TIGs in UCF. The reset signal is now registered in every module. ( ^3 e {9 \3 H2 R. x# n8 C. ?
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 3 J$ G/ ^8 d. \+ ]
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
6 s" J }2 A5 t: ]9 q# ~; {- Replaced `defines with localparams for Verilog.
! o/ n3 d/ l0 I8 x" k, J- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
6 \0 v; A& _. z6 q# z: {- Removed the UniSim primitive components declaration from VHDL modules.
0 K& B0 t, Z9 ?7 @" b. h6 z7 t) k- The signal "DLY_CAL_DONE" is now a port in the top module.
# {3 Y/ V1 K" |6 ~- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
- J5 \/ ?& [ s- q1 Z, b$ D( u- Added support for DDR Byte writes.
7 ], L+ W9 i( a: e- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
4 q/ b8 ^$ P. O, b7 ^a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ' J# O+ v' H; R- k1 }3 ]
b. WASSO is applied to all the memory interface signals.
4 u1 h Q' [+ R e7 f+ z: x( B( mc. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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