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chip123

這個版是熱門領域---EDA 達人愛好者的！你逛這一版，是因為你專業從事EDA 相關技術應用？還是只是業餘愛好EDA 者？:o
7 [$ B: n6 J  `. l& j$ E" C這版需要您熱情參與討論，與大家分享你的問題，你的經驗，你的工程師專業，你的技術鬱悶，你的技術欣喜！
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正面：abc1973：好網站是要靠大家維持的，這樣才會發揮Web2.0的真正功能，就是大家一起成長啦^^
. y3 l# C/ J! c3 t. `6 X反面：andy2000a：台灣的討論 好像比較難分享 如同一堆 rd   自認為自己know how  跟本不願和人分享

+ D+ f1 c& a) A" f1.討論主題：
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   你難道都沒有這些需求麼？不需自助助人麼？ 問題求助 好康相報 經驗交流 精華出售...
& n3 O, j" Q2 T3 B   這些技術領域還不夠寬廣？都不需要討論麼？  民意調查 經驗交流 議題探討 市場探討 ...

2.副版主人選：
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   本版先前頗有人氣！但可能因為尚未有正、副版主人選，以致未能持續討論風氣？哪幾位願意來身先士卒，組織社群，造福蒼生？
! D2 D& v/ f7 K$ N   誠懇呼喚以下高手如雲的大大（大俠）：
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   roger2003, henrylai, hgby2209, lcctsai, klim, nemo, leogao99, ty0001, hsd123, imems, edward0519, treebug, binjon, jordanplus, waynez, henrylai, 西湖水, ty0001, brian_shu, yeali, jlian168, staric, ryanchen, jimy, tengomark, chihsinchang (阿猛), scping, chjan, hycmos, waynez, hgby2209, kingfiretai, xiexie57, duckdh, ceusiin, dellmikkon, pheychang, taylor_su, richc, Y先生, jordanplus, brian_shu, huhu, star123, scounix, stella321, scounix, staric, d8731502, haha, treebug...

masonchung：討論區會有多少人參與要看大家能否在這裡得到收穫吧 夠專門領域的論壇會有更多專門領域的同好及專家前輩參與討論 板主的話應該有熱情再加上專業領域的人才都可以勝任阿

3.激勵方案：
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  如果你也有意加入團隊：12 位正副版大聯合發佈令
3 d/ a6 O- i# Y0 N. \& G3 @                                   chip123知識社群核心管理團隊組織運作草案  
9 d6 D* P# {4 t& E+ y& @- L                                   技術討論版各招募5位副版主，有意者請於各版以應徵版副發帖

  讓大家群策群力共同  為台灣論壇發聲...以技術定高下，以專業論輩份，以經驗帶成長，以感謝為鼓勵...
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  如果您希望這個版有所發展！並對你職場上有所幫助！請不吝進來報到！表示意見！熱情參與才會學得更多！

chip123

以下是Mentor Graphics upcoming IC-Focus U2U 使用者大會 希望能透過客戶彼此面對面的經驗分享，增加設計技巧，以期將產品的效能發揮到最高效益。

3 q$ S+ J' y8 y' l' ~. B$ qCall for Papers!

想和大家分享您的設計經驗及解決方案嗎！
您就是我們相中的專家！就是您！千萬別懷疑！

2 Y" U6 h& |% K3 I) y. z" @分享您創新的設計解決方案和成功挑戰困難的案例。
從下列主題中挑選出您欲分享的 Topics 及Abstract：
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	Incremental DRC		Resolution Enhancement Technology (OPC, Scattering Bar)
	Parasitic Extraction Solution		Formal Verification & Clock Domain Crossing
	Design for Manufacturing		Advanced Verification Methodology
	Analog/RF Fast SPICE Simulation		Logical Simulation
	Memory BIST, Boundary Scan, Scan Insertion, ATPG, Test Compression, Scan Diagnosis

jiming

有這麼多可以討論的... 昔日出現的大家卻不見了... 是都到別處看人家討論麼？
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想把你的設計經驗和大家分享嗎 ? 想告訴我們你如何突破設計挑戰嗎 ? 舞台是您的 ! :o
  {4 z% d9 w+ i& V' a$ O7 `6 Shttp://www.cadence.com.tw/cdnlive_2007/main_02.htm

Functional verification

Power-aware functional verification & modeling

Transaction-based verification, modeling & acceleration

Hardware/software co-verification - ISX

Verification planning and management

Testbench development and automation

Assertion-based Verification

Formal Analysis

Simulation debug and analysis

Analog-mixed signal system verification

Silicon debug in-circuit emulation

Platform VIP Reuse

Digital IC design

RTL synthesis

Formal verification

Low-power design/estimation in front end

Low power design implementation and analysis

Design for test/yield/manufacturing (DFT, DFY & DFM)

Constraints management and timing analysis

Hierarchical layout, prototyping, and planning

Physical optimization, routing and timing closure

Dealing with ECOs

Coping with variation during implementation

Signoff (timing, power and SI)

Physical verification (DRC, LVS, EM)

New technologies challenges

IP design and reuse

High-performance design

Custom IC design

Analog/RF parasitic extraction and simulation

High-frequency challenges and solutions

Statistical simulation

Circuit optimization

Full custom floorplanning

Physical automation/ optimization

Physical verification

Voltage drop/electromigration

Mixed-model/mixed-signal simulation and analysis

Test for analog/mixed-signal designs

IC 6.x Adoption

Deep submicron challenges/solutions

Modeling/characterization

Analog/Mixed signal methodology enhancement

RF Design methodology enhancement

Silicon-Package-Board

Front-end design capture

Constraint-driven design

Design partioning and reuse

Library and data management

Integration with PLM systems

Infrastructure and customization

Interactive and automatic routing

Design for manufacturing and testability

Signal and power integrity analysis

Simulation model development

Multi-gigahertz design

Design process and automation

Algorithmic-based model development

Designing in DDR2 memories

Silicon/Package co-design

Rapid feasibility prototyping methodologies

DFM verification of complex IC Packages/SiPs

Package-On-Package design techniques and challenges

RF SiP methodology enhancement

Special Interest

OpenAccess

Reliability modeling

Design for test/manufacturing and RET signal integrity

Design reuse strategies

Impact of standards on design optimization

Configuration management

Process design kit automation

Platform-dependent methodology flows

Linking of design and fab data to improve ramp yield

DFY/DFM optimization techniques and results

Interoperability