|
Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks+ G+ F+ y+ u/ Z; Y, p
然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack 9 y. x1 }3 F0 A+ o7 ?# P
之後卻有如下之 Meaasge:0 ^$ |/ ~: ~- V& {6 J: ]7 Z( |
) P, Q. P9 U( U+ _+ X. n5 M
******** Pin Access Analysis ******* ; h7 M/ V; L" Z
** # Cell Masters = 10002 Y7 l8 ~$ E1 ^4 t
** # Ports (logical) = 2500
6 i# Q7 O. P6 b" ~+ ^+ e9 A** # Pins (physical) = 2500
' a# \& ?1 @' _+ X** # Pins with no good access point on Grid (V&H) = 5 ( 0%)
! L% L, m0 j7 y% } K1 a+ c** # Pins with no good access point on Ver-Grid = 5 ( 0%)5 C( |: v( U0 P- \2 t
6 H) O7 d, m4 _& H" t* v
請問下面這兩句是代表什麼意思呢?( T2 W( B: k* A5 t- J" _
** # Pins with no good access point on Grid (V&H) = 5 ( 0%)
+ J- _# Q' _* K** # Pins with no good access point on Ver-Grid = 5 ( 0%)
8 k) G+ N s6 i* z1 o : t2 f, H; n% O+ D
若是代表有錯誤的話是否要 Fix 呢? |
|