You must be sure that, , t' {6 j% M" g$ c" T& Y& t# S$ j
1. your design output meets standard SVGA HSYNC/VYNC timing7 f: W7 T9 r# }+ l, ~% S
2. You must also set constraint on the ISE project, and check the timing report after 1 N& E& n0 Z" K( [$ }
the P&R is done. (also called STA timing report)0 j! A) S( s. {, |5 z. ~/ T8 B, F5 `( v
3. Sometimes, you must check the board, and I/O SSO issue(signal integrity....)