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Cadence SoC Encounter 8.1 Update Seminar! Y% ?0 r) E& {9 L! A: u
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2 r4 Y( d7 P3 n# [0 O, e3 n: v; I想了解Encounter最新8.1 版本強大的新功能嗎? 想知道Encounter 8.1如何協助眾多設計成功案例嗎? 我們將展現Encounter如何讓您的晶片設計smaller, cooler & faster,也提供您處理大尺寸晶片設計的解決方案,趕快參加Cadence益華電腦免費的Encounter 8.1 Update 研討會吧。4 i, @. J) V/ ^: r5 n! x; g0 t
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時間:- ]/ T( m) a; ?5 ]& \- e
9 I% A G- d* t' }Nov. 14, 星期五: 09:00am – 13:30pm $ S3 r6 X, S. W0 D g' C4 G# K
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新竹國賓大飯店13F 會議室A&B (新竹市中華路二段188號)3 @% e) {" |5 }" O! H
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7 `1 ~! a; u2 n名額有限,請即刻報名!(http://www.cadence.com/tw/events ... ion.aspx?eventid=16) & v4 S6 P5 ~" o: r
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" w, _! e8 R; W% @- o5 U2 I09:00~09:30 / Registration2 Y9 m1 \% J8 J; q0 D
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09:30~09:40 / Automatic floorplan for design exploration to get the best result X4 s X! M! ]8 w% `3 z" Q
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09:40~09:50 / Balanced clock tree to reduce process variation effects
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09:50~10:00 / 32nm support for the very advanced technology 7 m% ]% d, i/ P3 f# Z5 z
# P5 d( v+ z& A% l10:00~10:10 / Post route optimization and SI closure productivity & Q; }9 p* F9 u
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10:10~10:20 / 100% MMMC support in the entire implementation flow
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- y6 [% l1 m. n, r2 a10:20~10:30 / Dynamic power optimization and low power CTS for power reduction
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10:30~10:50 / Break
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10:50~11:00 / Encounter Power System for new generation power integrity analysis
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# V# x( B' }( C M11:00~11:10 / 3 very advanced statistic applications for better performance ( i P3 i0 _$ V7 `" }
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11:10~11:20 / Active Logic Reduction Technology (ART) to handle big chips7 I+ h+ P$ v6 C, x' r' p V. Z( O
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8 N6 J8 y) F; e/ l9 S11:20~11:30 / Constant run time and memory usage improvements
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11:30~11:40 / End-to-end parallel computing support1 L6 M1 G* K0 w$ @3 I4 t4 K
5 a, a3 t9 _; ]5 |, r11:40~11:50 / Encounter Foundation Flow for ease of use and productivity gain) e+ V0 e; A' Q k' R" E6 A9 ?) h7 A
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11:50~12:00 / Ending
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