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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用
# G0 @$ I: a3 K4 _Nwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.
7 ?, y$ A) L! [. [# }
' q1 |# ~3 f! p0 vDummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance
+ _5 g, P- O: [0 F/ v) cExtraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer
& M" \$ I( ?) S9 x Odummy, 為的是在CMP process時,有較佳的均勻性:
! @/ t( V, b% h" bDummy(or fill) metal is introduced in the interconnect process flow to enable uniform% T9 L T( K N& |& ~( K
thickness control in the CMP process. Dummy metal needs to be treated as floating metal
0 C& K( w9 f- v- s" j& X) }9 y; f1 Yunless it is intentionally connected to a constant potential. Floating dummy metal
- o# ~2 [+ E1 ]4 y8 t# k$ Ressentially acts as a capacitance divider.* _9 q) {) M/ M: @$ A
另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆9 H* E6 W- E @6 v; w- E* X% W
mos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保
# g/ ]8 L* h% |) j( z' L主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部
6 O) n# b- {8 X6 G- K1 F份).以上是我自己的想法,歡迎各位先進指教 |
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