|
這應該是APR的論文: i3 O4 U6 l0 A( e) B6 w! m
) E( z6 C" N. D6 T0 l" ?7 G# ?! {2 P& v3 S5 K& s) S% @. e6 `' Z
Abstract:
1 ?. O: y. [+ Q1 e: X5 R! tParasitic interconnect corner methods are known to
4 O! J7 E/ j- K: n. M8 [! b( mbe inaccurate. This paper explains the sources of their errors and6 s: N' t2 e+ D$ ]3 e' H
shows that errors in excess of 22% can occur in the predicted& C$ L2 ^" f1 W5 e: ^! r
corner delays of a multi-layer stage in the presence of process
3 L; l- \) Z: ^8 @& W/ T) `2 kvariations. It is shown that exhaustive corner search methods are
1 [% G; ?5 s, t2 Z" einfeasible in practice as they have an exponential complexity in
# Q4 p! O! ^1 Kterms of required SPICE simulations with respect to the number
' p) J0 I& f& t2 q, i+ A" pof layers a stage is routed through. This exponential complexity4 u8 s T' e, N4 \/ t
is reduced to a linear one with a new simulation-based search
7 z3 J' V9 n3 l) Bmethod with the aid of stage delay properties. The ideas behind
. V& o6 x+ f( ^+ L0 Ythe simulation-based methodology are shown to be expandable
0 Y" v1 D7 t; M% g/ zto an analytical-based multi-layer performance corner location7 W6 o# U+ d& n; Y$ A
methodology. The simulated best/worst case delays based on these
! b0 G- A- H$ c6 panalytical corners produce errors below 4% as compared to the& U& ~ F* d, ?. J9 b
exhaustive search simulation based method.# F9 G& y( X4 W
/ ^3 I: ]. @9 g: q) G% V
[ 本帖最後由 masonchung 於 2008-4-22 12:01 AM 編輯 ] |
本帖子中包含更多資源
您需要 登錄 才可以下載或查看,沒有帳號?申請會員
x
|