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8 Failure Modes, Reliability Issues, and Case Studies 228
2 F1 B$ [" i# x# e% Q2 _* x$ \8.1 Introduction 228
. r& w/ y( A5 S" s ^ {8.2 Failure Mode Analysis 229
& W9 U/ A% ]7 A4 ?$ K0 {8.3 Reliability and Performance Considerations 238
" ?( S9 U1 f$ Z, {6 k2 A8.4 Advanced CMOS Input Protection 239- q% e/ @$ V$ I% w9 H# n# |
8.5 Optimizing the Input Protection Scheme 242
* e8 X2 V+ c9 y3 n( j/ Y8.6 Designs for Special Applications 2491 Q, m8 o! y: {+ T& C
8.7 Process Effects on Input Protection Design 253' P3 ^/ w* ?& P: N9 {( E# y5 S, l$ k
8.8 Total IC Chip Protection 255: Z1 R% }+ J3 q; `7 y. b
8.9 Power Bus Protection 256 V9 Q' D0 M% H7 v9 r
8.10 Internal Chip ESD Damage 258
: R1 d7 L9 V$ D/ K: L* B8.11 Stress Dependent ESD Behavior 263. x. T- }* ?, L9 y! J3 `. X
8.12 Failure Mode Case Studies 267/ V, W8 V3 l& d: O7 e1 [
8.13 Summary 271
0 s- ~8 g- [/ p2 L* ~2 |3 ~Bibliography 272
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