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LOAD SDC FILE時$ V) [* Q9 [. r. g* l2 R0 a( h- i
Astro 訊息# M2 T9 i; b% }0 _" ^; B7 |! L
---------------------------------------------------------------------------8 B w1 a2 F4 R: l
Info: starting Tcl processing# c9 ?. Q- b, U& ^5 s
Info: building design object name tables : a0 o; Y3 L# w, c* `
Warning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)9 j! |( j! \1 H( F) A* n Y
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
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----------------------------------------------------------------------------$ r3 P! K! ?* G2 ]6 F; ^1 I
SDC FILE
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set_multicycle_path 9 -through [list [get_pins \
! T8 }' q: ]8 S! b9 ~2 A* E: p{TOP/test/mul/A[26]}] [get_pins \
f3 R, C/ R6 L- l- W. C{TOP/test/mul/A[25]}] [get_pins \
' j- C# H/ `* ], F- V M# J& {4 B H3 D
: \% X: _9 \- C8 @9 f$ ?* i9 L
-----------------------------------------------------------------------------
4 B7 x( {5 t# i% I) v0 WVerilog File% W" I0 I# W1 Z% n7 p' o& E. U
4 h$ K. u p: k uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
) W% C ^7 f0 u2 @9 Q/ D1 e" _ icwAeYfNum[18:0]), .C(ae_avg) ); |
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