徵求6X64記憶體VHDL

w10789173 · 發表於 2008-3-8 00:01:38

徵求記憶體6-bit data in 64個字組,不過不要用陣列的方式,很感謝大家提共意見,不過都不是實際記憶體電路的VHDL,我想要的是一個column decoder,一個row decorder,使用port map latch 64個,輸出要使用三態閘,個人想法如下:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY memory_64 IS
PORT(
   mem_in : IN    std_logic_vector ( 5 DOWNTO 0 );
   mem_out  : OUT std_logic_vector ( 5 DOWNTO 0 );
   clr_l : IN    std_logic;
   mem_addr : IN    std_logic_vector ( 5 DOWNTO 0 )
);

-- Declarations

END memory_64 ;

--
ARCHITECTURE arch OF memory_64 IS
-- column decoder
component mem_coldec
PORT(
   col_addr : IN    std_logic_vector ( 2 DOWNTO 0 );
   col_sel  : OUT std_logic_vector ( 7 DOWNTO 0 )
);
end component;
-- row decoder
component mem_rowdec
PORT(
   row_addr : IN    std_logic_vector ( 2 DOWNTO 0 );
   row_sel  : OUT std_logic_vector ( 7 DOWNTO 0 )
);
end component;
-- latch array
component latch_cell
   PORT(
      clr_l : IN    std_logic;
      col_sel  : IN    std_logic;
      row_sel  : IN    std_logic;
      data_in  : IN    std_logic_vector ( 5 DOWNTO 0 );
      data_out : OUT std_logic_vector ( 5 DOWNTO 0 )
   );
end component;

signal smem_out : std_logic_vector ( 5 downto 0 );
signal scol_sel,srow_sel : std_logic_vector( 7 downto 0 );
BEGIN
  u_0 : mem_coldec port map(mem_addr( 5 downto 3 ),scol_sel);
  u_1 : mem_rowdec port map(mem_addr( 2 downto 0 ),srow_sel);
  g0 : for i in 7 downto 0 generate -- column generate
g1 : for j in 7 downto 0 generate -- row generate
      u_2 : latch_cell
      port map(
      col_sel => col_sel(j),
      row_sel => srow_sel(i),
      data_in => mem_in,
      data_out => mem_out(i)
      );
end generate;
  end generate;
END ARCHITECTURE arch;
不過模擬很久,始終沒辦法寫進我想要寫的位址,試寫了很久,但是始終寫不出來,所以請大家幫個忙,不然那些範例網路上都有,有點急,請大家廣發建議,感謝大家!

w10789173 · 發表於 2008-3-9 08:05:19

Thanks for your solutions!

That is what i want it!

This question already slved, please do not reply anymore.

Thanks again...

aiken · 發表於 2008-3-9 03:15:53

http://tiny-tera.stanford.edu/ti ... ibm-ssram-dist-1.1/

You are designing ASIC ram? or use it in FPGA?

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徵求6X64記憶體VHDL

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