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回復 4# 的帖子
1. Using technology file to create a library
3 r) U: n, f5 y2. Do stream in with cell type definition file. Specify some special layers' number. IE : Boundary Layer is 63.( M6 j2 u" u; \# q5 r
3. Open new created library, and create some metal blockage if need.: c4 H4 v4 K/ P e& R* g$ u. t: c+ _
4. Do smash if need.
, N. W# L- q3 R5 N, K- Y5. remove some unnecessary extension txst. IE VDD ---> VDD
: Z) U8 ~0 @! y/ K% @; `6. Define power,ground as well as in/out port4 b& R4 c; ^4 G
7.Extract Blockage,Pin and Via by using command auExtractBlockagePinVia.0 n1 n2 g$ W& A" U# h3 A
3 b5 {8 m, G4 x$ R1 B
The processes listed above is my method to do data preparation. Maybe someone know other best way for this issue. Please share it with us.
: C8 n2 v: I0 u: {: H6 g9 }+ }2 w-->我要怎麼做才可以把 ANALOG中 重複性較高的部份交給 APR去做? a; r" _8 q+ s0 g" b: f1 E+ ? ]2 A
I don't understand your question. Do you want APR toll to place and route your analog block? It is a bad idea if your answer is yes. |
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