Which verification elements does your team use on your current design project?

ranica

Pls check all that apply, unless you don’t know?

innoing123

針對10奈米  FinFET 設計，Mentor 和 TSMC 還改進了Calibre 填充解決方案。Calibre YieldEnhancer 中 SmartFill ECO 的功能支援「隨時填充 (fill-as-you-go)」工作流，以確保IP和其它設計模組在設計過程中都能準確地呈現。當部分設計被修改時，SmartFill ECO功能可重新填充僅僅受影響的那部分，從而最小化轉回時間 (turnaround time)。同樣的，為在諸如TSMC10奈米這樣的先進工藝節點上維持設計層級實現高效的佈線後模擬， Calibre LVS 也被改進了。
: J# J) b4 {3 c5 Q6 m% R" J
兩家公司還聯手調整了 Mentor® Olympus-SoC 的佈線和路由系統讓它能滿足 TSMC 的10奈米 FinFET 的要求。為了能用於10奈米 FinFET，數據庫、佈線、時鐘樹合成、提取、優化和路由引擎都做了重大的改進。

- l2 M7 J  P: \( W; E) Y  g/ p為了確保10奈米 FinFET 設備的準確的電路類比，Mentor 與 TSMC 合作讓 BSIM-CMG（伯克利共多柵極電晶體）和 TMI 模型在 Analog FastSPICE 平臺（如AFS Mega）上能用於高速設備和電路層模擬。Calibre xACT™ 提取產品和 Calibre nmLVS™ 產品也支援新的10奈米 FinFET 模型。
( G& m! C, t% b' K( I: i+ j
因Mentor 和 TSMC在設計賦能方面的合作讓客戶取得成功的案例，將於9月30日在San Jose Convention Center（聖若澤會展中心）舉行的TSMC的開放創新平臺生態系統論壇(Open Innovation Platform Ecosystem Forum)會議上講述。瞭解詳情，請參訪TSMC網站 www.tsmc.com 。

innoing123

Mentor Graphics 與 TSMC 合作為10奈米推出 IC 設計和結束基礎架構
/ i# }  E7 j; |% _  O) N. k
俄勒岡州威爾遜維爾2014年9月27日電 /美通社/ -- Mentor Graphics Corp.（納斯達克：MENT）今天宣佈該公司與 TSMC（臺灣積體電路製造股份有限公司，簡稱台積電）達成10奈米(nm) 的合作協定。為滿足用於早期客戶的測試晶片和IP（互聯網協議）設計起動的10奈米鰭式場效電晶體 (Fin Field-Effect Transistor；FinFET) 的工藝要求，已經改進了物理設計、分析、驗證和優化工具。基礎架構包括 Olympus-SoC™ 數位設計系統， Analog FastSPICE (AFS™) 平臺（含AFS Mega）和 Calibre® 結束解決方案 ( Calibre® signoff solution )。
, G, W9 I1 l9 V1 x* E
TSMC 設計基礎架構行銷部 (Design Infrastructure Marketing Division) 高級總監 Suk Lee 表示：「TSMC 和 Mentor正在進行廣泛的工程工作，以便讓雙方的客戶都能很好地利用先進的工藝技術。每一個節點都需要進行許多創新才能滿足新的物理要求、提高客戶設計賦能 (design enablement) 的精確度，與此同時性能更優、轉回時間更短。」
' {4 I1 |' s; X% n3 x' Z8 s- Y7 g
Calibre 提供佈線形狀的全色彩能力，以幫助設計者指定符合10奈米規則要求的設計艙(cockpit)之外的色彩分配。針對制定積體電路佈線圖，改進後的Calibre RealTime 產品能進行互動的色彩檢查，同時利用晶片廠認可的Calibre結束平臺能使用所有制定佈線工具進行設計。

ranica

Senior Physical Design Engineer
+ Y" ?6 u+ E+ T; @; w公      司：A famous IC company
) i5 h  P' c1 e5 V& s( x$ e2 Y6 U工作地点：南京

6 y1 l0 D, _* V/ p- X+ \- N) pKey Responsibilities  
* W; j* r: @0 TDepending on experience, key responsibilities will involve some of the following:  
) M, Y& g* F( C! q$ t+ MIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
- D! H4 _. x' F4 x3 _8 W% o6 GAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
Leading a team of physical design engineers and resolving the technical related issues.  
Crosstalk analysis, power analysis, and static timing analysis.  
3 U# [6 m- E9 m$ z( SWrite scripts in Tcl to improve productivity.  
6 r# E  R; i; q. e
职位要求
" t$ f( d0 @  zExperience: 5+ years in physical implementation engineering   
Essential skills  
* Y7 @0 L1 T5 L3 E7 ^4 T# v/ ZMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills  
9 p2 ~9 D7 {- _1 d3 R* EExperience with Magma or Synopsys place-and-route tool set and physical design project implementation.  
% k% j7 c' A) Z" NGood programming skill. Capable of writing Tcl or Perl.  
Familiar with synthesis, static timing analysis.  
7 Z5 U2 u# O% K4 HSelf-motivated team worker, good verbal and written communication skills in English.  
3 d: f. ]# n# m8 I- N; yTechnical and team leadership proffered. Previous management experience highly desired.  
/ R4 h: e# V3 A4 [  E& n; {Experience with synthesis, DFT, and verification is preferred.

ritaliu0604

Position Requirements:  
1. Experience:  
- Minimum experience required: 10 years  
- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments.
+ Y& z( t: d% }; x5 J# `, B- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.
- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired
- Strong verbal and written communication skills in English are required  
* _; @1 q" e8 J" P- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must
$ `1 @! O. B3 _: v- K- Hardware verification, including knowledge of HDL simulators and debugging simulations
- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.
- Knowledge of embedded systems and software development for SoCs is a plus
. ~* M; G( e$ g- g/ Y! Q2. Education:  
Ideally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts  
3 }+ t" N' l% E6 R3 N9 V2 v3 c- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience).
- f5 X& q) l* N& ]3. Travel of 30% of the time should be expected.

ritaliu0604

Staff Hardware Based Design and Verification Engineering Lead

3 u1 M: D  L, b' T7 [5 j1 S公      司：One world top EDA company
9 d: w# a, n) _工作地点：上海
' Q0 v' c; j6 o6 S, \
4 k/ f/ x2 z( I( q" S' MPosition Description:  
1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx  field application engineers and customers alike.
' R4 w" L+ z% D* r1 F+ D; w& y# i
2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers:
* Q; l' T: G( U) [, T. b(1) xx  Palladium HW Acceleration Platforms
(2) xx Acceleratable Verification IP portfolio
(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis
(4) HW/SW Co-verification solutions for SoC designs