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實驗平台~7 R- i- ~ E7 J, C% [, l
「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA
3 S6 Z7 g3 c+ F9 o在建構的過程中(僅放入cpu跟memory ip)
, H0 r3 G9 @5 p5 vno reset vector has been specified for this CPU
* I5 _0 i& \% \& {! S. j4 s/ Dno exception vector has been specified for this CPU
* y1 q: [) w/ u2 `$ L! }; F! k這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎
; F% I. T8 e8 n+ F# W5 Z試過
6 ~& p( S0 z) ]% p$ Yon chip memory$ f: w( G$ _% g# @
sdram8 G+ @7 T( k6 d/ {- t- M
用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)7 [7 @7 w0 a8 W3 B% N# O2 f9 w
no reset vector has been specified for this CPU
, l% x$ C2 A( q- b6 o5 {* \; P% \no exception vector has been specified for this CPU. Z; D; n! P% ~7 S3 `* |- k' @, q" s: B
總是會有一個沒辦法去除(先選的訊息會被消除)
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有人有在玩10.1版嗎?請多多幫忙~~; B T6 @+ T) g2 A
4 _* x! ~* R* i0 _5 ]3 o目前打算~改用10.0sp1跟9.1sp2試試看5 d6 K4 m9 Y) g3 `
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