[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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. {) A1 W4 [, R因為無法回覆, 所以開新文回答....
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6 J6 C5 y6 Y- Y& P- Y% pVerilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
# R& k2 H( B* B! s. m– Logical operators: !, &&, ||
! T; s6 l! B1 j! p: y, R# D– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
– Logical shift operators: >>, <<
– Conditional operators: ? :
" `- p" |  M: S5 T* r– Duplication operators: {n{ <exp> <,<exp>> *}}
! C5 [2 x4 q# Y& K" R1 h7 H– Concatenation operators: {}
. d5 I& S4 g! y給你參考一下