請教90/65奈米,SOC Tape-out一次NRE大約多少

ajack

如題

0 Y( X" u& x" z6 ]請教業界各位先進
目前的chip開發,需要多少投資?
6 [+ X2 J2 A+ k首先是假設 Febless design house.
1 ]5 y/ a, E/ {2 F+ B( j# ~0 _2 Q自家由algorithm 到 RTL simulation 完成
後端包給 backend service 公司 (layout, mask, Fab, assembly..)
以 ARM9 or ARM11, AMBA2.0 為platform
5 ^" @8 ]8 C/ v那麼
  (1)90奈米, NRE大概多少?
; n) I- l8 y. ]4 x. G  (2)65奈米, NRE大概多少?
: o& b1 w7 Q5 x6 M/ n& R  (3)或是您知道其他製程, NRE大約多少...
9 d" }4 F9 T; Z/ J2 N+ J5 y
謝謝

hkgcrcom

頂頂更健康，支持一下。                                  qq自由幻想外掛

semico_ljj

need 1M dollar?

alex3010

sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!

alex3010

if the ARM and AMBA is hardcore,
" ], d% \* F2 U" cbasically 65nm-->USD$1M above and 90nm-->700K above
- I( \% o( r/ A  e) vand base on different foundry has difference price!
this price did not include any specific IP like TV encoder, decoder, vedio codec....
% j' m0 u& }9 [3 _# w, ]and did not include the ARM licensee...
7 }0 X5 q# G7 J' a1 t+ [& dactually! it is not so much IC design in Taiwan tape out 65nm till now!

ajack

Well,

( w! f+ H3 A9 d: [I just estimate the investiment of a ASIC team.
0 A2 x  L: f2 J  a$ Dnot servey for a project.
So, I just want to know the range of NRE.

4 U/ l7 ~( L: e$ [: _For example, It will be
(1) 5,000,000 NT$ ?
(2) 8,000,000 NT$ ?
(3)10,000,000 NT$ ?
(4)12,000,000 NT$ ?
, s' B9 ~* @, J# g0 x9 E* V(5)15,000,000 NT$ ?

4 u0 o6 p6 Z" N) d7 jSure, I understand following things:
- full set mask cost more
- PLL/LVDS... analog IP are extra cost
- pin-count and area also influence cost
- different package also cost different

  h9 U4 y2 ?' u" g; ?. STherefore, if really need information for estimate,
just for example.
Let's assume a SoC for FullHD TV application
it will include
  - ARM AMBA
  - DDR2 I/F
  - GPIO, IIC,...
  - LVDS out (dual link)
. v4 [, q  V) h0 w4 ?  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
  - 12bit ADC, 10bot ADC x2
+ _% P  z0 ?( |, I8 F: s  - PLL/DLL
/ E/ [1 w- _9 K3 N  - 256 pins 以上

5 j0 `5 W4 C9 a. F' nThan,... any idea about NRE fee?
again, I just want to know the range

elroy216

Which design service company you will go to?
* g2 b6 ]6 P! Q( _How many mask layers it will be?
! t$ r- X  ~9 |( f1 ?$ x" q0 W8 PBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
How many chips you need? A full set mask or MPW?
What package you need?