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Bit rate and protocol independent clock and data recovery1 \* l* F; S2 \3 l# O, n
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A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use
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in optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been
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" T ^1 [" g8 s6 f7 ^4 U: Zextended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). # k# _) \9 X% \
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This architecture guarantees reliable clock synchronisation of the input data with different line / @7 {, `: p0 G4 d( C3 H# _3 \
0 k# ]4 D% z6 ]# B0 S0 v+ Tcodes over a frequency range spanning multiple octaves* V/ N6 l" v8 w- z3 m- }1 D* y8 \7 l
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