LVS問題 望大大指點

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使用LEdit90的LVS時，顯示This file is Binary.LVS can not perform iteration.無法進行對比，這是怎麼回事呀

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我宅了一周 沒想到栽在路徑上  萬分感謝 ！！！！！！！！！！

m851055

與非門2 files name改為英文名稱.......................

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版圖
3 `6 U9 B+ ]3 H4 s9 q  M* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;
* TDB File:  G:\tanner\Nand2.tdb
3 C9 h! k% w8 R* Cell:  Nand2        Version 1.07
* Extract Definition File:  G:\lights.ext
% z6 Z; H7 C! Z+ j, C& G7 r* Extract Date and Time:  05/25/2009 - 15:05
* Y" ^7 D9 u+ F0 v* P& F* Warning:  Layers with Unassigned AREA Capacitance.
*   <N Well Resistor ID>
9 s! ~: |1 e% V% p) S+ \) e  r*   <Poly Resistor ID>
2 |2 L+ v8 O4 C: `! b*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
*   <P Diff Resistor ID>
9 w! \2 g# q1 ^9 m$ W*   <P Base Resistor ID>
% w; X  P  Z3 f" w3 O  q. o. a* Warning:  Layers with Unassigned FRINGE Capacitance.
' K' N" L* i# v: D2 z8 [5 n8 H*   <N Well Resistor ID>
5 Z/ t$ y" J# x8 {& V" {9 m*   <Poly Resistor ID>
- G$ A7 x* B" s, K$ G# n) l$ h*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
*   <P Diff Resistor ID>
3 m+ G! x. ^7 o  S3 i*   <P Base Resistor ID>
: t/ n4 j% `* Z" O6 e*   <Pad Comment>
9 S4 `+ n' X. z*   <Poly1-Poly2 Capacitor ID>
$ q, z' S& U! V2 H( c* Warning:  Layers with Zero Resistance.
- P" o  ^4 }( Q1 d/ c*   <NMOS Capacitor ID>
*   <PMOS Capacitor ID>
$ F! j+ U+ V* {; I( I*   <Pad Comment>
*   <Poly1-Poly2 Capacitor ID>

# l% e! g* r6 e; n* NODE NAME ALIASES
*       1 = B (12,-14)
*       2 = A (-16,-18)
*       3 = OUT (-2,-21)
) J7 Q: a) I" P/ M*       4 = GND (-30,-35)
*       5 = Vdd (-32,14)
M1 Vdd B OUT Vdd PMOS L=2u W=6u
* M1 DRAIN GATE SOURCE BULK (3 -3 5 3)
3 y& G4 h% ~: d2 eM2 OUT A Vdd Vdd PMOS L=2u W=6u
* M2 DRAIN GATE SOURCE BULK (-5 -3 -3 3)
2 c) K. U# u5 {" q0 j+ b6 L4 XM3 OUT B 6 GND NMOS L=2u W=6u
1 C4 r% e! Y; y4 O/ Q* M3 DRAIN GATE SOURCE BULK (3 -31 5 -25)
M4 6 A GND GND NMOS L=2u W=6u
* k1 C4 X, p% N  b( c0 D* M4 DRAIN GATE SOURCE BULK (-5 -31 -3 -25)
; r) @% e0 o9 q, J8 E* Total Nodes: 6
+ B8 W, {; J2 |- B, e, s& q0 i* Total Elements: 4
" D3 s7 n( D# v% L( K, a* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
( q9 M) a# \4 U7 @9 h* E5 L.END

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原理圖
* SPICE netlist written by S-Edit Win32 7.03
& ^, r' k/ x. v! q* Written on May 27, 2009 at 16:57:24
* Waveform probing commands
' M1 m  O; t% `+ H1 `.probe
.options probefilename="G:\tanner\Nand2_1.dat"
+ probesdbfile="G:\與非門2.sdb"
  }5 y  [% Q6 t: ~+ probetopmodule="Nand2"
9 J7 d' C* s3 e/ c, J* Main circuit: Nand2
) o4 s! ]* y8 e$ FM1 OUT A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Gnd B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
! K- P; R& z! |+ q2 ^2 R$ _M3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
5 Y, b$ x2 {7 m: ?7 W1 C* End of main circuit: Nand2

m851055

是比對檔案中路徑的問題，若有需要詳細說明把netlist PO上來................