LVS問題 望大大指點

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使用LEdit90的LVS時，顯示This file is Binary.LVS can not perform iteration.無法進行對比，這是怎麼回事呀

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我宅了一周 沒想到栽在路徑上  萬分感謝 ！！！！！！！！！！

m851055

與非門2 files name改為英文名稱.......................

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版圖
* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;
* TDB File:  G:\tanner\Nand2.tdb
* Cell:  Nand2        Version 1.07
( P+ m4 ^9 R( y; R7 p$ p" K6 G" B5 K* Extract Definition File:  G:\lights.ext
1 q+ A) H  i8 y4 F* l9 D* Extract Date and Time:  05/25/2009 - 15:05
* Warning:  Layers with Unassigned AREA Capacitance.
*   <N Well Resistor ID>
*   <Poly Resistor ID>
*   <Poly2 Resistor ID>
+ M* B) @) ^# [. y+ e*   <N Diff Resistor ID>
! F; w, R4 q% b) y*   <P Diff Resistor ID>
6 N! ?, M& F9 Y*   <P Base Resistor ID>
* Warning:  Layers with Unassigned FRINGE Capacitance.
*   <N Well Resistor ID>
*   <Poly Resistor ID>
*   <Poly2 Resistor ID>
*   <N Diff Resistor ID>
7 @) k8 I5 P) O: u% b4 ]! O8 H*   <P Diff Resistor ID>
) ]1 Q" w+ s. O1 ?7 s*   <P Base Resistor ID>
: v& X3 `' A( q9 [: Y9 y$ x*   <Pad Comment>
7 F" N( \4 l! n3 n0 z( v*   <Poly1-Poly2 Capacitor ID>
% w5 f  K/ T% P1 h* Warning:  Layers with Zero Resistance.
) S2 Z+ p/ z9 ^4 T% n$ O2 A*   <NMOS Capacitor ID>
# L1 ?/ z3 S; I: |; R) p( \' l*   <PMOS Capacitor ID>
% o+ F7 j) |* P5 P0 I7 E" a+ z+ V- f*   <Pad Comment>
7 `! w+ `7 y. T2 F, E% [5 X8 z*   <Poly1-Poly2 Capacitor ID>
! k0 @1 \1 S! G9 B" V# ]
* NODE NAME ALIASES
) `7 g* a. {) [% v1 Y, y*       1 = B (12,-14)
6 {7 R. q$ L& K! H' u2 ]*       2 = A (-16,-18)
*       3 = OUT (-2,-21)
*       4 = GND (-30,-35)
. l6 c0 G. U/ E% A) U+ G! S$ f*       5 = Vdd (-32,14)
M1 Vdd B OUT Vdd PMOS L=2u W=6u
( `1 i. W% c# P2 P+ p& l/ C6 j* M1 DRAIN GATE SOURCE BULK (3 -3 5 3)
M2 OUT A Vdd Vdd PMOS L=2u W=6u
* M2 DRAIN GATE SOURCE BULK (-5 -3 -3 3)
% {5 [, D2 m; `M3 OUT B 6 GND NMOS L=2u W=6u
+ o' U1 h$ U1 R2 ]+ _7 j( u4 y* M3 DRAIN GATE SOURCE BULK (3 -31 5 -25)
M4 6 A GND GND NMOS L=2u W=6u
8 n; j" V4 m# j( ~8 o; g4 ^- A* M4 DRAIN GATE SOURCE BULK (-5 -31 -3 -25)
3 R2 M( @' Y( I* ?  B* Total Nodes: 6
  R# S& K0 t: q: c8 L% h, P* Total Elements: 4
* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
8 s9 g! n& e: q- @8 o9 `& o, ?.END

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原理圖
* SPICE netlist written by S-Edit Win32 7.03
% q, s" j9 X( X0 z( n  [* d* Written on May 27, 2009 at 16:57:24
* Waveform probing commands
.probe
.options probefilename="G:\tanner\Nand2_1.dat"
+ probesdbfile="G:\與非門2.sdb"
8 r9 w' H. m6 c7 w+ i2 l+ probetopmodule="Nand2"
* Main circuit: Nand2
M1 OUT A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
8 w, t4 [: m+ x6 o+ [" f: j5 XM2 Gnd B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
* End of main circuit: Nand2

m851055

是比對檔案中路徑的問題，若有需要詳細說明把netlist PO上來................