Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

0 g; _3 m& ?8 K( X0 H8 k! w0 oKaran Bhatia and Elyse Rosenbaum
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
. U2 f  z- G8 F$ _4 U4 R1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
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Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
5 L. e. }; Y3 Y; {8 m4 y( N5 bcapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
- z0 x! u* U# F+ I; k- n/ ?% Nperformance of the structures investigated herein.

yoyoseven

謝謝你的分享
現在急需esd的防護方式

hing

很棒的參考資料，謝謝分享！

allenearl

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  |8 A5 k# M; R# U6 ~7 M& P+ q www.gooemc.cn

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

majorchen

權限不夠,真想看看layout guide要注意什麼...
& Q3 G* i) R: {真是可惜...

mousestack2003

感謝大大分享這些資料∼
' f2 m& l4 v/ N: Z6 N4 Z) P' L4 l
. @9 ~/ `/ V" p  [4 x讓我們了解led的一些事情∼

semico_ljj

The dual-diode circuit has been found to be a suitable
& m, l/ m" M$ w2 f5 W- A0 eESD protection circuit for GHz-frequency CMOS
I/Os [1]. Layout-optimized ESD diodes provide a
8 v7 o2 D9 J# F$ ]8 x3 Y* rhigh protection level per unit capacitance (C),
( Z& a* Q4 `' i; Z. y$ j5 bminimizing the performance degradation they induce
on high frequency I/O pins.