Berkeley的一篇博士论文_Jitter Reduction on High-Speed Clock Signals

hitxiaojun

This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
/ F5 O! d7 f+ I! P2 `Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
& G1 n6 z3 f6 p$ ^3 |+ Fon par with commercially available PLLs, while being relatively simple to design and use as
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does
8 {& J+ _! S: w# c+ J4 Knot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
0 n; i( |1 d' b+ e9 q! \% V, ^) Othe following sections the effects of jitter, present methods to reduce jitter, and application
of the JAC will be discussed.
! d. n/ j& o0 }8 E

遊客，如果您要查看本帖隱藏內容請回復

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝！
* b' `3 ]3 R) M8 w

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝！

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝

alienwarejian

谢谢
6 Y- T8 M. A9 }6 j/ O谢谢

ja1688888

剛好需要看PLL jitter 學習一下 感謝

starfish311

回復 1# hitxiaojun


/ N5 X& M" a: k    謝謝你的分享，希望會有所幫助

lyx1982

谢谢分享！收藏了！！！

xp212125o

thank you~
  N8 n/ K: d- i感謝分享
6 z6 c& i$ v0 P1 {* V- l正好有需要

anita66

感謝大大無私分享, 不知道有沒有跟Thomas Lee的論點是否相同??3Q~

eceking

可惜沒足夠的錢幣............................................................!

ychchip

jitter is important issues in analog ic design.  it must be carefully designed including path match and high speed.

donnie

Thanks for Sharing!
  u3 P2 U$ \2 y$ s& L9 n. zThanks for Sharing!

donnie

Thanks for Sharing
Thanks for Sharing

b56389

多看看別人所推薦的paper
7 S( C8 f+ ?/ ^研究其的看法與理論
; ~  D0 W& ~( [; b( {. r, s相信對增進自己的實力有幫助的

godman

謝謝你的分享，希望會有所幫助。

planet1114

最近在工作上一直被noise所困擾,
; c0 u: {1 i# X2 a/ y下來看看能不能從這有新的啟發.
, l( ^6 O& F: D- C6 B5 @先謝啦

anita66

Wow, 新的耶?!真是太讚了, 先下來study看看, 有機會在跟大家分享心得, 3Q~

liyao

> < 我很少上來 沒錢下載 怎麼辦呀!!

liyao

剛好工作上碰到jitter measurement問題,下載參閱一下,感恩!!