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Analog / Mixed Signal Examples; ^* V1 @( B+ u6 B
; |5 B0 f& m x3 hBehavioral Models of ADCs
% r: _" I7 k y\ams\sampling\; sampling_101;; D# H& B7 l L* V4 l
Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2; % Q! j" {* {. D
Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3;
+ z* E K {. _* G Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4;
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Behavioral RF. U9 y8 n5 Z, o. b w/ n
Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;& |; u" b8 B5 R `8 ?
6 p, q7 K9 U+ }0 Q1 C6 }. C4 rPLLs
! q2 b" I" Z" M- G9 p VCO with phase noise $ cd 5 C0 X; ^2 }2 @% l$ T
Pll with freq domain instruments $ cd \ams\pll; # i* t6 ] u! J5 n1 y/ J2 x
Pll fractional with analog compensation $ cd \ams\pll; 2 e6 i! i( i/ y/ j/ K: z
Pll fractional with digital compensation $ cd \ams\pll;
/ I% E+ V1 F: W+ m! \+ T! U Pll optimization (Nonlinear Control Design) $ cd \ams\pll; # u& t/ p+ a: k! A/ P7 X3 i& N5 z
Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing;
- K! R8 U" a/ o" _, p Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
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