時間
- N* V5 j( {1 y V; r | 活動內容
) r& J/ P9 R! ]8 b' ?' Q A8 t | 主講人
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1:00-1:30 - ], t2 M" b9 f9 x1 C+ t
| Registration2 `. V$ a& K' z1 S
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1:30-1:35 & V7 t( g% ~3 f0 n8 n8 @/ s; ?+ r2 t
| Introduction: Agenda, who's here,
3 v! N( h7 e7 z! rwhat do we do?
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1:35-2:05
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Note: Why prototype?, \* `" T0 S* I8 H' D- ~; g; J
ASIC Verification Options4 C, [: c5 e5 b" ]% W& n
| Ashok Kulkarni,Technical/ c# i8 E b/ y9 |* Z
Marketing, Synplicity) g, _# L$ w! G9 [
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2:05-2:50 1 {/ ]# w! q# @& Y
| V5 for ASIC Prototype8 ^& Q( u" g+ m+ _' I- Q) l
| Simon Ho, Corporate Solution marketing Manager, Xilinx. [# B8 [6 t! k" y$ P
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2:50-3:10
$ c+ o/ g( T! o6 q3 c3 L6 h | Break# d0 H$ o4 g8 {! v3 z5 |; M, @) }4 e% p
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3:10-3:55 & H# N6 I0 d, W- K1 X+ \
| Creating a platform around you FPGA(s)
' o8 o% x1 F+ O y/ ` | Ashok Kulkarni,Technical
% M6 U' }8 O1 L7 r9 \Marketing, Synplicity6 k( d g# G, ?! u, V+ p
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3:55-4:25
$ [( n' s/ N6 I9 _! J; }1 L! f | Faster FPGA Implementation
1 n0 V% S/ D* n- E | Simon Ho, Corporate Solution marketing Manager, Xilinx
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4:25-5:00
' E0 }- [$ n) U% p8 \: h) c; T; s5 ` | Making the ASIC design ready for FPGA - HAPS live flow demo8 s2 f! s; R' U1 k- X
| Freddy Lin, ASIC Verification Specialist, Synplicity Taiwan0 D* ]+ F7 Q' t/ q! }* }4 y; E
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5:00-5:30 . i, A! [$ R/ C" P& y% W: S
| Q&A, Lucky Draw and Wrap-up
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