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MPMC2's features including: & n5 ?% F# s% O: e) y% ]
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Number of ports (Scalable from 1 to 8) 5 }$ c; Z* ]: }. Z% y) P2 O
Type of memory (e.g. DDR, DDR2, user defined)
( j, T* {1 j7 ~- n$ e! V6 q! PWidth of memory (8, 16, 32 or 64-bit) 8 J$ E# |9 y0 \% E
Various Port Interface Modules (Processor Interfaces, DMA engines, Standalone, etc) $ g! o( f4 \, n3 R1 j4 Z, m# v9 _
Memory device part number 7 O( z* Y2 I0 X, }% D
Arbitration methodology
5 m$ U9 Z7 |1 e: mSelectable pipeline stages for frequency matching
% I6 o. [9 b1 s7 jExample system topologies using MPMC
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MPMC2 extends the range of possible solutions by providing designers additional design capability for higher performance and/or advanced system topologies. System topologies can be built utilizing different types of Port Interface Modules (PIMs) on a per-port basis.+ Y0 R6 Q/ y- f8 p2 W1 l9 `. D+ f
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" @8 N& S6 A* a; u' Q" pThese seven types of PIMs are presently supported:
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3 A6 Q$ @% w+ R5 ?IBM™ CoreConnect™ Processor Local Bus (PLB PIM)
) }- _, @, S6 X- q4 `IBM CoreConnect On-chip Peripheral Bus (OPB PIM)
' S! r+ a0 ]- e1 i SPPC405 Instruction Side Processor Local Bus (ISPLB PIM)
4 G) o0 v- d4 L+ @0 a# [8 e' \PPC405 Data Side Processor Local Bus (DSPLB PIM) # x- Y% M/ d$ i5 c' D: F# [2 j/ K
Communication Direct Memory Access Controller (CDMAC PIM) 6 |4 U. F4 Q: T8 O- D) q. t- I
Native Port Interface (NPI PIM)
: I/ T) k5 G! r" H/ qXilinx MicroBlaze™ CacheLink (XCL PIM)
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The four pictures below represent a small sampling of possible system topologies: ; P, {2 e) [ R. F+ g$ X
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& Q- G n$ u& a5 H7 u, eFigure 1. Example MPMC2-based system topologies.
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Applications* F1 O/ N+ q5 D& }
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MPMC2 enables users to deploy Xilinx products for many new applications in the storage, server, telecommunications, and wireless market. As shown by the above topology examples, the MPMC2 enables designers to create solutions for DSP, high performance multi-processor based systems and standalone applications. Based on the architectural needs, the MPMC2 configuration GUI provides designers options to choose various memory interfaces and system topologies that build upon the standard capabilities provided within Xilinx Platform Studio.! g8 p/ l# f1 p4 H6 @/ @
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