Xilinx Virtex5 FPGA 結構與特性

小朱仔 · 發表於 2008-3-26 00:28:20

*Objectives- a8 E3 g5 ~4 L
After completing this course, the student will be able to:, ]2 F6 B9 o8 z* K9 m. |$ ~( I  ~
Describe both the feature enhancements of the V5 over the V4,( s7 V7 O6 P  l6 h
and
9 p/ m  I9 O9 o+ }; ^8 B' `9 @1 f7 INew architectural features of the V5$ a& K0 [% @" j. [
Have a fundamental understanding of how these features can be
, H9 u5 r, A, `$ v3 f- vleveraged to bring about timing closure., z6 H! G* L, K) V- j3 X
*Agenda
* V7 C, r7 l5 C3 O7 g4 aOverview (15 minutes)
: Y# p* S1 v5 k% B" O0 h, k; O2 yBrief Description of Differences between V4 and V5 (30 minutes0 S2 R( @+ \7 _/ S& Q& \7 m$ t6 }
V5's new PLL and Use with DCMs (45 minutes)
' D' }' A- ?9 r, ZLab 1 – Introduction to the PLL/Architecture Wizard (30! K3 U8 Z: b/ g8 H! f2 S
minutes)" ]5 j. \3 [4 Q* R" I+ ^
Improved Features in V5 (30 minutes)
Lab 2 – Leveraging Improved Features (45 minutes)

hqioan · 發表於 2008-7-2 13:04:38

下載來看看...希望有幫助....最近在學

moneyhqq · 發表於 2009-1-4 19:31:14

hao hao hao hao hao hao hao hao

ch1122 · 發表於 2009-1-9 13:51:49

下載來看吧...多增加一點知識也是不錯...
感謝分享..希望以後有機會能用上

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Xilinx Virtex5 FPGA 結構與特性

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