Calibration techniques in nyquist AD converters

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Table of contents
5 l# {+ s: X; k! ^1 KList of abbreviations
List of symbols
: B, |. {1 T2 m5 J6 m; FPreface
! H1 _6 G* [& O1 Introduction 1
1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
' I( Q8 @! z' E4 h8 ]3 S' s1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
$ t) J+ T. N9 f: _# @- V  }5 A2 Accuracy, speed and power relation 7
. s+ I" @( F0 d9 h4 M% ~" u2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
0 r) b8 M% g' K7 c( Q: F2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
" z' f+ L  [+ A6 a6 l: B2.2.2
# F. w: C7 g& w: a6 a( z; e2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8 U0 y2 C' K) Q& S2.5 . . . . . . . . . . . . . . . . . . . . . 15
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 c0 e5 V4 h( ]4 L3 A/D converter architecture comparison 21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
$ \8 Q6 M  _0 }* z, U: o7 Z3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
CMOS technology trends
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Table of contents
; D( I' A5 A6 q0 O2 l3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
3.7.2 Architecture comparison as a function of the resolution . . 57
3.7.3 Architecture comparison as a function of the sampling speed 65
4 I9 y& _5 ~" R/ b' J1 v& V3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
; Z/ N$ L) G% b! W  V7 ?4 Enhancement techniques for two-step A/D converters 67
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
, o4 Y4 A% x5 x, s4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
2 }: g# r: m& n8 E5 h+ f4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
' z+ l$ y8 t$ C* }$ |8 a2 Z  Y  R& C8 n4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
5 r* g" }% E# h+ D7 n( ?4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
0 y- v! p+ i) v6 E: F# j6 k. X4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
9 w+ Z  k3 Z" ~0 y8 M8 Z4 M4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
# Y/ Z: [- B0 F0 j0 _8 v# t9 C$ B4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
6 e8 H+ `& C4 e4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
4.5.4 Offset extraction and analog compensation . . . . . . . . 91
1 {9 y' Y" Q. f' C/ Y0 Q4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
  L1 _9 w4 i! c! C' a* W4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 A 10-bit two-step ADC with analog online calibration 103
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
: b" E! R5 @7 w' T0 P& E( g5.2
1 G4 [# Z6 R2 b+ p5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
- L6 j- J- C. \7 v! i' a7 j5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
' w; ~# L4 E6 d- b) }1 V5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
! S, y3 c" O0 p. f1 ?5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
- d. N, L* N" n1 t6 i( G! _5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
( x8 C; V# W* u# B1 X4 Z0 s. S: l5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
5 d9 n# ?! ^8 p- [8 ?$ Y5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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/ Q7 N/ I# I- e' s( ~8 o1 nTwo-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
! R5 Y: L/ T9 c, UTable of contents
5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
3 p# w6 n# q. i/ T, h5 m. {& C5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
- s, L1 L7 w8 ]5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
; I- J! n" @! a( `1 a6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
7 A low-power 16-bit three-step ADC for imaging applications 149

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tuza2000

good material !!!