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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用1 x& U+ g9 ?4 Y3 N8 G
Nwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.
1 x% R3 f, s# \( O4 W7 }
/ S8 E% O$ d: z! q4 b) ]8 JDummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance
+ Q3 l' W2 f7 G/ Y2 HExtraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer 1 y: _8 X o% j+ R: |: [: c% z
dummy, 為的是在CMP process時,有較佳的均勻性:( e; O; _. A9 ?+ D' D* U- ?) k' ~
Dummy(or fill) metal is introduced in the interconnect process flow to enable uniform
7 s" a2 b" l o2 u1 a* [5 B thickness control in the CMP process. Dummy metal needs to be treated as floating metal
7 b4 K0 m+ d6 H7 D" wunless it is intentionally connected to a constant potential. Floating dummy metal 5 J; U1 m* m8 D
essentially acts as a capacitance divider.- i; m1 b% [5 V1 ?- ]
另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆
; g4 H ^# T6 M! bmos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保7 Q2 H( b# r; `
主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部3 s3 e) _1 F$ M. \8 ]
份).以上是我自己的想法,歡迎各位先進指教 |
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