|
我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用
3 ] l9 p" [0 S; A$ j/ k& K! VNwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.: x' K. P8 Z3 J; S4 ]5 I, \
/ `- l2 Q U0 y& i. q1 T5 R. z/ C; Z
Dummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance : o$ A/ v6 S/ v% A K# b2 k
Extraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer 4 T A, D7 A; U9 N
dummy, 為的是在CMP process時,有較佳的均勻性:
1 y: c2 J& m; o* f* ?Dummy(or fill) metal is introduced in the interconnect process flow to enable uniform
3 e6 y# e+ c# B8 {) N% w2 @ thickness control in the CMP process. Dummy metal needs to be treated as floating metal 1 L! p; G; k/ v F7 b# G2 }4 o
unless it is intentionally connected to a constant potential. Floating dummy metal 2 j2 y" V- m5 K" X0 P8 @
essentially acts as a capacitance divider.) H1 [! j. F7 Z4 r, I, ~' [
另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆
; c7 G5 {! M' S) Gmos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保
; P5 Q. y# v; u: E+ y主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部$ s) p6 B* I% _+ e
份).以上是我自己的想法,歡迎各位先進指教 |
|