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這應該是APR的論文* b# k, Z5 y k. c
3 R1 ~) F( ?$ w, A; B
) Q; g% t( u9 zAbstract:& Y: T) C7 r0 A/ z9 P+ ]
Parasitic interconnect corner methods are known to _1 P% Y$ Q* T8 d
be inaccurate. This paper explains the sources of their errors and
6 J% `$ Q% d9 d! r4 H- q. v: a% A6 Gshows that errors in excess of 22% can occur in the predicted
6 c2 o# V# e' V9 @3 O4 {corner delays of a multi-layer stage in the presence of process3 N8 P( E- H4 P1 z6 Z8 d
variations. It is shown that exhaustive corner search methods are5 d9 x' a( I* m! `' X. Z
infeasible in practice as they have an exponential complexity in
- g1 T( b1 `2 Iterms of required SPICE simulations with respect to the number
- r- b3 u/ X0 `4 ]* B& Oof layers a stage is routed through. This exponential complexity
1 m; j: [* X, N5 U3 x* His reduced to a linear one with a new simulation-based search
0 l U& r4 K# u' ~' ymethod with the aid of stage delay properties. The ideas behind' E& e7 I7 K9 c$ Q- |
the simulation-based methodology are shown to be expandable
8 ]" v/ E4 f: X" ^( t* nto an analytical-based multi-layer performance corner location1 i E$ ?1 M) G: B
methodology. The simulated best/worst case delays based on these# h3 w. \: N+ ~4 _, h5 R8 J
analytical corners produce errors below 4% as compared to the- a$ U4 O1 E8 S: p
exhaustive search simulation based method.- r5 d# s# \; Q0 P& P6 q
4 C# B/ ?6 V# [$ Y[ 本帖最後由 masonchung 於 2008-4-22 12:01 AM 編輯 ] |
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