verilog 觸發問題

peliuya

今我欲使 sys_signal 此輸入訊號在正緣時，使 rst_B1 訊號為 High。
8 I& e  l, I4 S( C% N0 p( B
5 y- }6 T# W8 }! s! f% G0 @. a/ Y正緣過後（即下一個 system clk(50 MHz)），rst_B1 復歸為 Low。

sys_signal 此訊號為  60 Hz , Duty ratio 為 50 ％ 的方波

請問應該如何撰寫此段程式？

nesty.tseng

always @(posedge CLK_50M or negedge PORB)
begin
: \$ i; L6 T% ^8 d$ p5 ]6 b& G% Q5 I! B  if(!PORB)
3 z# H2 P5 |; N8 ]# v    sys_signal_d1 <= #1 1b'0;
2 I8 b# O/ ^5 b4 j0 w0 b+ l  else
7 q) l7 F4 A" C5 q9 P: X& f. s; E    sys_signal_d1 <= #1 sys_signal;
end
& R" g, \# _" H- `
, q$ H! }( E7 P& e& k& Jassign sys_signal_pul = sys_signal & ! sys_signal_d1;
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" a" N) H* a, p0 c# o+ \5 o% Walways @(posedge sys_signal or negedge sys_signal_pul)
4 J+ \1 [; i6 A, S+ J1 ]begin
" C6 Y4 i, k( _7 Z+ k- Z  if(!sys_signal_pul)
    rst_B1 <= #1 1'b0;
5 P% {- w7 m: ~! Z9 H7 M/ b  else
    rst_B1 <= #1 1'b1;
' Q" R; s( w8 h3 J! H8 W! ?3 Pend