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LOAD SDC FILE時
0 S7 m' z5 h/ R4 h& sAstro 訊息' \( J$ M7 a+ ^, s1 N* b7 P& y
---------------------------------------------------------------------------) S& H5 i8 U% y. t! m
Info: starting Tcl processing7 v" G/ _& q$ p8 }. [
Info: building design object name tables
- K/ C, Q9 S* h' Y FWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)8 n; ~' H. [ I$ n; X
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
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4 f# M* W6 b3 f2 r5 H2 @SDC FILE
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set_multicycle_path 9 -through [list [get_pins \. \) G$ o5 |: ?5 F% L O
{TOP/test/mul/A[26]}] [get_pins \0 s: S& q* S5 N& m
{TOP/test/mul/A[25]}] [get_pins \# V3 V# e' P4 z, V6 M% r( u
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+ p# O: A+ k- z+ {: yVerilog File
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uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
$ D( ^# I3 N- Q, d icwAeYfNum[18:0]), .C(ae_avg) ); |
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