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回復 #1 option318 的帖子
回復 #1 option318 的帖子, f8 g/ l' Y' x+ d% ~
(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一5 Y i$ I: r1 e {4 S' ~
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump0 Z% c0 B3 g' x9 P1 e& Y2 @
pll ,且亦有unstability issue0 A" W7 B- `3 V
(see Charge-pump phase lock loops paper by Gardner T5 _# M$ e+ _+ n& ^
IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)$ Q' w! n B$ Z! L- D, Y b/ s
(2) loop BW is related to jitter (or phase noise) ,and locking time
2 Z) r& W4 X4 g y% lso you have to consider loop BW from jitter & locking time spec
5 h% z! g. D8 y# a, u. P& g* t(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq) ?, X' e$ k% X, J
(4) In my opinion ,gain margin is not considered in pll design |
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