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Senior Physical Design Engineer
/ M/ P/ |, Q! E; k公 司:A famous IC company
9 Z6 H2 _$ T9 g5 h工作地点:南京
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/ V) Z1 d1 t6 y/ b% S5 |+ H, [Key Responsibilities
( g# z6 ^# v9 J6 Y! ~2 qDepending on experience, key responsibilities will involve some of the following: * b7 e6 ]* P& R* c4 W; Z& d9 \
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. ) }5 q7 G0 G6 c
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed. " k# V* A+ |9 J+ D( o, ]8 V" u
Leading a team of physical design engineers and resolving the technical related issues.
- P$ \& M' @, h% A% Y+ R5 v3 WCrosstalk analysis, power analysis, and static timing analysis.
8 X8 A; N. m+ a+ sWrite scripts in Tcl to improve productivity. & {5 N. q' w, [( m% r( V3 l% [
. ~) t& R5 {* y, `Experience: 5+ years in physical implementation engineering 3 b5 H- ]: s0 i. ~& v
# E' @. l$ `: \# C% O+ `+ LEssential skills
# u! C' R0 C# T8 @& P. T( D- yMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 1 g: s( `* H5 ?- ?
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. & }2 C5 `, z+ F
Good programming skill. Capable of writing Tcl or Perl.
8 F- d- O9 o& h9 c8 NFamiliar with synthesis, static timing analysis.
, [% ^/ J, z7 ]% p0 X& sSelf-motivated team worker, good verbal and written communication skills in English. % v/ f; e) J/ w) {) V/ L- k1 K
Technical and team leadership proffered. Previous management experience highly desired. & p+ n* L; E1 v% S$ P, Q
Experience with synthesis, DFT, and verification is preferred. |
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