Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

2 @, Z2 x- c" p6 ?( }) kKaran Bhatia and Elyse Rosenbaum
# ^  v+ N, N6 l9 RDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
- w, w: p( G* c# |, B1 h- w1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
5 K7 e/ x. \: o8 |' N
3 f  P3 r2 l$ a, I9 EAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
; F# [3 X) z0 cinvestigated. The current compression point (ICP) is introduced to define the maximum current handling
9 R* Z8 a( v" _) L6 ~! A/ Xcapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
performance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
4 V8 K* [$ F1 ^ESD protection circuit for GHz-frequency CMOS
I/Os [1]. Layout-optimized ESD diodes provide a
0 S8 m5 {/ g& l0 S3 yhigh protection level per unit capacitance (C),
% ^3 x: E2 F. n9 ^3 o6 j* mminimizing the performance degradation they induce
on high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼
* \/ t7 \7 l* ]+ H
- W4 w* u. G" M! r讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
- c. u& F2 A( E) a小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
1 i/ _" ?- R& h4 [: ~0 {) i: d www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
' S$ R( @  P4 S5 d. X7 `現在急需esd的防護方式