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Layout Guidelines for Optimized ESD Protection Diodes
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% H3 _( Z& t4 k' g1 N, C2 OKaran Bhatia and Elyse Rosenbaum
9 _+ O9 T( H. O. E; Y5 {Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
4 L! ?: L- e6 m( X1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu2 s, d4 j' j) n& S- v
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Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are$ H8 d* K* W6 v
investigated. The current compression point (ICP) is introduced to define the maximum current handling# t$ }) A6 B' Y6 f7 S
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the/ @: a$ W- R5 ^
performance of the structures investigated herein. |
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