Design of High-Voltage-Tolerant ESD Protection: r6 ]% b; z# N5 j' |$ ^. d- F' L; d
Circuit in Low-Voltage CMOS Processes $ V7 d; V4 E. s" w 7 T2 K; m) E- p! HIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 1, MARCH 2009 ; V( i7 m" a2 m, B$ M. H9 u ( }, B ^% ]! r+ L5 T