|
4#
樓主 |
發表於 2013-12-12 09:14:21
|
只看該作者
Senior Physical Design Engineer$ s4 W5 p5 x5 ?8 H
公 司:A famous IC company4 X. v; A6 o2 ~9 E$ O
工作地点:南京4 b# m/ Y/ I. A! p
. m& ?1 C& c4 DKey Responsibilities % X" ]7 b. S$ j7 \! K
Depending on experience, key responsibilities will involve some of the following:
3 W8 {6 y. I* N* e- B# qIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
2 p: g- H: `& z `As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
6 C3 g' q! h, y2 A8 ~% O( A% TLeading a team of physical design engineers and resolving the technical related issues.
2 H# L2 A, J+ |* E: j/ tCrosstalk analysis, power analysis, and static timing analysis. ( q8 u; T7 ]) k; e2 e
Write scripts in Tcl to improve productivity. / n! X' Y" W9 h3 y+ o( F
3 W( ^0 D$ ~; }# Z% a: ~) n* N
职位要求: B8 J8 h8 s( ?0 g0 E# n. W7 C
Experience: 5+ years in physical implementation engineering ) S+ M* ^( ~% @9 N
Essential skills
+ g# N* `8 R+ w1 G5 c( s$ N( s2 `0 fMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills : k5 z/ h% U4 v( L& m' A
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. 8 o6 s$ `& {6 ~
Good programming skill. Capable of writing Tcl or Perl. 6 m1 b; C" x/ y z1 T
Familiar with synthesis, static timing analysis.
- G& s% U: g4 Q; v0 m% t8 Z' e) PSelf-motivated team worker, good verbal and written communication skills in English.
( |8 z/ N/ a$ ]6 r+ b4 Y" [Technical and team leadership proffered. Previous management experience highly desired.
, W" W8 D# ~6 }Experience with synthesis, DFT, and verification is preferred. |
|