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Design and Analysis of Technology Errors0 C0 [6 D s1 c4 ? Z9 L
for CMOS Poly-silicon Capacitor3 y" o) B4 _. I6 G" g6 |; b
ZHUZhang-ming ,YANGYin-tang , ZHANGChun-peng , FUXiao-dong
' A/ T9 `" a5 J. x: H(Microelectronics Institute ,XidianUniversity,Xi’an 710071 , China)$ V6 ~* N2 B9 e* G( [1 _2 }
Abstract : The technology errors of CMOS poly-silicon capacitor are analyzed .The effect of various errors introduced. Y& U. X! \- c& X1 @, o( w
during fabrication on CMOS poly-silicon capacitor is discussed .Based on the improved design of unit-capacitors , the+ i! Z) _$ K4 w% w7 _; k
common-centroid floorplan of poly-silicon capacitor is presented . On the proposed capacitor design way , the CMOS" G% q* |8 L2 c: F: [* t( f: \# E- V
switch-capacitor bandpass filters is implemented using 0.6μmCMOSDPDMprocess .Themeasured results of filters show
, v% y! H* T! s! X$ qthat the proposed capacitor designway can be used to design high accuracy capacitors ,and applied to the design of submicro- m; ]: C; d1 |# z+ h8 r
and deep sub-micro analog integrated circuit ." n6 o+ D1 p1 S
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[ 本帖最後由 sjhor 於 2007-5-17 10:37 PM 編輯 ] |
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