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Bit rate and protocol independent clock and data recovery
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Abstract2 d, V9 y+ t T0 M" z' a
% F: Y o9 W% \A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use
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in optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been
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extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs).
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# k& s$ {4 m m9 M! A8 IThis architecture guarantees reliable clock synchronisation of the input data with different line 0 r" C" G1 L6 o, k
* z. T- C: v- a- o3 acodes over a frequency range spanning multiple octaves& c6 j+ T. R$ a* Z
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