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Bit rate and protocol independent clock and data recovery7 w8 M( f/ {& u* _9 ^
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Abstract
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A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use & \$ o! C1 b% J( ^7 Q/ f
' J. }0 R$ Q/ L$ { _in optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been
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& _2 b3 e# U4 X. @extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs).
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This architecture guarantees reliable clock synchronisation of the input data with different line ( w' d! `8 m, b9 s) f8 l# W
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codes over a frequency range spanning multiple octaves
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