[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

因為無法回覆, 所以開新文回答....
: V2 }$ v$ k) \ABT={2'b00, DATA, 4'b0000};

Verilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
– 2’s complement operators: +, -, *, /, %
/ D4 b1 X; U* c' A; Y: P– Relational operators: >, <, >=, <=, ==, !=, ===, !==
& w6 c5 P. w+ h' G– Logical shift operators: >>, <<
– Conditional operators: ? :
. f/ x7 x9 K7 m% H% O. z: r– Duplication operators: {n{ <exp> <,<exp>> *}}
– Concatenation operators: {}
. T7 Q: U6 q" p3 Q& R# z; D. L- C4 G給你參考一下